Home
last modified time | relevance | path

Searched full:plla (Results 1 – 18 of 18) sorted by relevance

/linux/sound/soc/tegra/
H A Dtegra_audio_graph_card.c102 * PLLA in tegra_audio_graph_update_pll()
127 "Update clock rates: PLLA(= %u Hz) and PLLA_OUT0(= %u Hz)\n", in tegra_audio_graph_update_pll()
130 /* Set PLLA rate */ in tegra_audio_graph_update_pll()
134 "Can't set plla rate for %u, err: %d\n", in tegra_audio_graph_update_pll()
220 /* PLLA */
229 /* PLLA */
238 /* PLLA */
/linux/drivers/clk/renesas/
H A Dclk-r8a7779.c30 * (PLLA = 1500) (PLLA = 1600)
66 * MD PLLA Ratio
88 const char *parent_name = "plla"; in r8a7779_cpg_register_clock()
92 if (!strcmp(name, "plla")) { in r8a7779_cpg_register_clock()
H A Dclk-r8a7778.c46 if (!strcmp(name, "plla")) { in r8a7778_cpg_register_clock()
47 return clk_register_fixed_factor(NULL, "plla", in r8a7778_cpg_register_clock()
61 "plla", 0, 1, in r8a7778_cpg_register_clock()
/linux/Documentation/devicetree/bindings/clock/
H A Dvt8500.txt59 plla: plla {
/linux/arch/arm/boot/dts/vt8500/
H A Dwm8650.dtsi86 plla: plla { label
124 clocks = <&plla>;
H A Dwm8505.dtsi89 plla: plla { label
120 clocks = <&plla>;
H A Dwm8850.dtsi89 plla: plla { label
141 clocks = <&plla>;
H A Dwm8750.dtsi92 plla: plla { label
130 clocks = <&plla>;
/linux/arch/arm/mach-at91/
H A Dpm_suspend.S658 /* Save PLLA setting and disable it */
664 /* Save PLLA settings. */
717 1: /* Save PLLA setting and disable it */
721 /* Disable PLLA. */
782 /* Restore PLLA setting */
785 /* Enable PLLA. */
/linux/drivers/clk/
H A Dclk-sp7021.c18 /* special div_width values for PLLTV/PLLA */
51 u32 p[P_MAX]; /* for hold PLLTV/PLLA parameters */
626 hws[PLL_A] = sp_pll_register(dev, "plla", &pd_ext, PLLA_CTL, in sp7021_clk_probe()
/linux/drivers/clk/bcm/
H A Dclk-bcm2835.c538 * loop. Bits 13:14 of ANA1 (PLLA,PLLB,PLLC,PLLD) have been re-purposed in bcm2835_pll_get_prediv_mask()
1673 * PLLA is the auxiliary PLL, used to drive the CCP2
1681 .name = "plla",
1697 .source_pll = "plla",
1707 .source_pll = "plla",
1717 .source_pll = "plla",
1726 .source_pll = "plla",
/linux/include/linux/clk/
H A Dat91_pmc.h139 #define AT91_PMC_PLLADIV2 (1 << 12) /* PLLA divisor by 2 [some SAM9 only] */
197 #define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
/linux/drivers/clk/tegra/
H A Dclk-tegra210.c336 /* PLLA */
827 * PLLA
831 static void tegra210_plla_set_defaults(struct tegra_clk_pll *plla) in tegra210_plla_set_defaults() argument
834 u32 val = readl_relaxed(clk_base + plla->params->base_reg); in tegra210_plla_set_defaults()
836 plla->params->defaults_set = true; in tegra210_plla_set_defaults()
845 plla->params->defaults_set = false; in tegra210_plla_set_defaults()
852 _pll_misc_chk_default(clk_base, plla->params, 0, val, in tegra210_plla_set_defaults()
856 _pll_misc_chk_default(clk_base, plla->params, 2, val, in tegra210_plla_set_defaults()
860 val = readl_relaxed(clk_base + plla->params->ext_misc_reg[0]); in tegra210_plla_set_defaults()
863 writel_relaxed(val, clk_base + plla->params->ext_misc_reg[0]); in tegra210_plla_set_defaults()
[all …]
H A Dclk-pll.c579 * PLL_P_OUT1 rate is not listed in PLLA table in _calc_rate()
/linux/sound/soc/codecs/
H A Drt5682s.c1685 SND_SOC_DAPM_SUPPLY_S("PLLA", 0, RT5682S_PWR_ANLG_3,
1850 {"ADC Stereo1 Filter", NULL, "PLLA", is_sys_clk_from_plla},
1852 {"DAC Stereo1 Filter", NULL, "PLLA", is_sys_clk_from_plla},
1854 {"PLLA", NULL, "PLLA_LDO"},
1855 {"PLLA", NULL, "PLLA_BIAS"},
1856 {"PLLA", NULL, "PLLA_RST"},
2297 /* Look at PLLA table */ in find_pll_inter_combination()
2313 /* Find a combination of PLLA & PLLB */ in find_pll_inter_combination()
2382 "PLLA: fin=%d fout=%d m_bp=%d k_bp=%d m=%d n=%d k=%d\n", in rt5682s_set_component_pll()
/linux/arch/arm/mach-tegra/
H A Dsleep-tegra30.S368 * enable PLLP, PLLM, PLLC, PLLA and PLLX.
705 /* disable PLLP, PLLA, PLLC and PLLX */
/linux/arch/arm/boot/dts/renesas/
H A Dr8a7778.dtsi503 clock-output-names = "plla", "pllb", "b",
H A Dr8a7779.dtsi585 clock-output-names = "plla", "z", "zs", "s",