| /freebsd/sys/contrib/device-tree/Bindings/sound/ |
| H A D | ti,pcm512x.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Animesh Agarwal <animeshagarwal28@gmail.com>
13 - $ref: dai-common.yaml#
18 - ti,pcm5121
19 - ti,pcm5122
20 - ti,pcm5141
21 - ti,pcm5142
22 - ti,pcm5242
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| H A D | pcm512x.txt | 8 - compatible : One of "ti,pcm5121", "ti,pcm5122", "ti,pcm5141",
11 - reg : the I2C address of the device for I2C, the chip select
14 - AVDD-supply, DVDD-supply, and CPVDD-supply : power supplies for the
15 device, as covered in bindings/regulator/regulator.txt
19 - clocks : A clock specifier for the clock connected as SCLK. If this
20 is absent the device will be configured to clock from BCLK. If pll-in
21 and pll-out are specified in addition to a clock, the device is
24 - pll-in, pll-out : gpio pins used to connect the pll using <1>
26 given pll-in pin and PLL output on the given pll-out pin. An
27 external connection from the pll-out pin to the SCLK pin is assumed.
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| /freebsd/sys/contrib/device-tree/Bindings/c6x/ |
| H A D | clocks.txt | 1 C6X PLL Clock Controllers
2 -------------------------
4 This is a first-cut support for the SoC clock controllers. This is still
10 - compatible: "ti,c64x+pll"
11 May also have SoC-specific value to support SoC-specific initialization
12 in the driver. One of:
13 "ti,c6455-pll"
14 "ti,c6457-pll"
15 "ti,c6472-pll"
16 "ti,c6474-pll"
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| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | qoriq-clock.txt | 5 multiple phase locked loops (PLL) to create a variety of frequencies
14 --------------- -------------
21 - compatible: Should contain a chip-specific clock block compatible
22 string and (if applicable) may contain a chassis-version clock
25 Chip-specific strings are of the form "fsl,<chip>-clockgen", such as:
26 * "fsl,p2041-clockgen"
27 * "fsl,p3041-clockgen"
28 * "fsl,p4080-clockgen"
29 * "fsl,p5020-clockgen"
30 * "fsl,p5040-clockgen"
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| H A D | brcm,iproc-clocks.txt | 4 Documentation/devicetree/bindings/clock/clock-bindings.txt
8 LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL
11 Required properties for a PLL and its leaf clocks:
13 - compatible:
14 Should have a value of the form "brcm,<soc>-<pll>". For example, GENPLL on
15 Cygnus has a compatible string of "brcm,cygnus-genpll"
17 - #clock-cells:
18 Have a value of <1> since there are more than 1 leaf clock of a given PLL
20 - reg:
22 clock control registers required for the PLL
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| H A D | baikal,bt1-ccu-pll.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-cc
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| H A D | silabs,si5351.txt | 5 https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
8 clocks. Si5351a also has a reduced pin-count package (MSOP10) where only
10 generators can be found in [1].
15 - compatible: shall be one of the following:
16 "silabs,si5351a" - Si5351a, QFN20 package
17 "silabs,si5351a-msop" - Si5351a, MSOP10 package
18 "silabs,si5351b" - Si5351b, QFN20 package
19 "silabs,si5351c" - Si5351c, QFN20 package
20 - reg: i2c device address, shall be 0x60 or 0x61.
21 - #clock-cells: from common clock binding; shall be set to 1.
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| H A D | silabs,si5341.txt | 6 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
8 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
10 https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
13 clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which
14 in turn can be directed to any of the 10 (or 4) outputs through a divider.
15 The internal structure of the clock generators can be found in [2].
17 dividers and automatic input selection, as described in [3].
20 The driver can be used in "as is" mode, reading the current settings from the
21 chip at boot, in case you have a (pre-)programmed device. If the PLL is not
33 - compatible: shall be one of the following:
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| H A D | fsl,qoriq-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,qoriq-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
15 multiple phase locked loops (PLL) to create a variety of frequencies
24 --------------- -------------
30 The clockgen node should act as a clock provider, though in older device
36 - items:
37 - enum:
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| H A D | sprd,sc9860-clk.txt | 2 ------------------------
5 - compatible: should contain the following compatible strings:
6 - "sprd,sc9860-pmu-gate"
7 - "sprd,sc9860-pll"
8 - "sprd,sc9860-ap-clk"
9 - "sprd,sc9860-aon-prediv"
10 - "sprd,sc9860-apahb-gate"
11 - "sprd,sc9860-aon-gate"
12 - "sprd,sc9860-aonsecure-clk"
13 - "sprd,sc9860-agcp-gate"
[all …]
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| H A D | baikal,bt1-ccu-div.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit Dividers
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
20 later ones are described in this binding. Each clock domain can be also
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| /freebsd/sys/contrib/device-tree/Bindings/usb/ |
| H A D | nvidia,tegra124-xusb.txt | 8 --------------------
9 - compatible: Must be:
10 - Tegra124: "nvidia,tegra124-xusb"
11 - Tegra132: "nvidia,tegra132-xusb", "nvidia,tegra124-xusb"
12 - Tegra210: "nvidia,tegra210-xusb"
13 - Tegra186: "nvidia,tegra186-xusb"
14 - reg: Must contain the base and length of the xHCI host registers, XUSB FPCI
16 - reg-names: Must contain the following entries:
17 - "hcd"
18 - "fpci"
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| /freebsd/contrib/bc/tests/ |
| H A D | all.sh | 3 # SPDX-License-Identifier: BSD-2-Clause
5 # Copyright (c) 2018-2024 Gavin D. Howard and contributors.
7 # Redistribution and use in source and binary forms, with or without
13 # * Redistributions in binary form must reproduce the above copyright notice,
14 # this list of conditions and the following disclaimer in the documentation
20 # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
24 # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
[all...] |
| /freebsd/sys/contrib/device-tree/Bindings/phy/ |
| H A D | nvidia,tegra210-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xus
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| H A D | nvidia,tegra124-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 is controlled by a HW block referred to as a "pad" in the Tegra hardware
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
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| H A D | nvidia,tegra124-xusb-padctl.txt | 6 is controlled by a HW block referred to as a "pad" in the Tegra hardware
11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
28 tree binding in this document uses the term "port" to refer to the logical
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| /freebsd/sys/dev/firmware/xilinx/ |
| H A D | pm_defs.h | 2 * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
4 * SPDX-License-Identifier: BSD-3-Clause
32 /* Version of APIs implemented in ATF */
117 /* PLL control API functions */
272 * @PM_RET_ERROR_TIMEOUT: timeout in communication with PMU
273 * @PM_RET_ERROR_NODE_USED: node is already in use
325 * @PM_PLL_PARAM_DIV2: Enable for divide by 2 function inside the PLL
326 * @PM_PLL_PARAM_FBDIV: Feedback divisor integer portion for the PLL
327 * @PM_PLL_PARAM_DATA: Feedback divisor fractional portion for the PLL
328 * @PM_PLL_PARAM_PRE_SRC: Clock source for PLL input
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| /freebsd/sys/dev/clk/allwinner/ |
| H A D | ccu_a13.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
6 * Redistribution and use in source and binary forms, with or without
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
47 #include <dt-bindings/clock/sun5i-ccu.h>
48 #include <dt-bindings/reset/sun5i-ccu.h>
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| /freebsd/sys/arm64/qoriq/clk/ |
| H A D | lx2160a_clkgen.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
6 * Redistribution and use in source and binary forms, with or without
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 #define PLL(_id1, _id2, cname, o, d) \ macro
67 PLL(QORIQ_TYPE_PLATFORM_PLL, 0, "platform_pll", 0x60080, plt_divs);
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| /freebsd/sys/contrib/device-tree/Bindings/ufs/ |
| H A D | ufs-qcom.txt | 3 UFSPHY nodes are defined to describe on-chip UFS PHY hardware macro.
10 - compatible : compatible list, contains one of the following -
11 "qcom,ufs-phy-qmp-20nm" for 20nm ufs phy,
12 "qcom,ufs-phy-qmp-14nm" for legacy 14nm ufs phy,
13 "qcom,msm8996-ufs-phy-qmp-14nm" for 14nm ufs phy
15 - reg : should contain PHY register address space (mandatory),
16 - reg-names : indicates various resources passed to driver (via reg proptery) by name.
17 Required "reg-names" is "phy_mem".
18 - #phy-cells : This property shall be set to 0
19 - vdda-phy-supply : phandle to main PHY supply for analog domain
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/power/reset/ |
| H A D | keystone-reset.txt | 3 This node is intended to allow SoC reset in case of software reset
14 - compatible: ti,keystone-reset
16 - ti,syscon-pll: phandle/offset pair. The phandle to syscon used to
17 access pll controller registers and the offset to use
20 - ti,syscon-dev: phandle/offset pair. The phandle to syscon used to
22 in order to use mux block registers for all watchdogs.
26 - ti,soft-reset: Boolean option indicating soft reset.
29 - ti,wdt-list: WDT list that can cause SoC reset. It's not related
32 in format: <0>, <2>; It can be in random order and
34 reset watchdogs and can be in random order.
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| /freebsd/sys/contrib/device-tree/Bindings/clock/ti/davinci/ |
| H A D | pll.txt | 1 Binding for TI DaVinci PLL Controllers
3 The PLL provides clocks to most of the components on the SoC. In addition
4 to the PLL itself, this controller also contains bypasses, gates, dividers,
8 - compatible: shall be one of:
9 - "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX
10 - "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX
11 - reg: physical base address and size of the controller's register area.
12 - clocks: phandles corresponding to the clock names
13 - clock-names: names of the clock sources - depends on compatible string
14 - for "ti,da850-pll0", shall be "clksrc", "extclksrc"
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| /freebsd/sys/contrib/device-tree/Bindings/media/i2c/ |
| H A D | adv7343.txt | 3 The ADV7343 are high speed, digital-to-analog video encoders in a 64-lead LQFP
4 package. Six high speed, 3.3 V, 11-bit video DACs provide support for composite
5 (CVBS), S-Video (Y-C), and component (YPrPb/RGB) analog outputs in standard
10 - compatible: Must be "adi,adv7343"
13 - adi,power-mode-sleep-mode: on enable the current consumption is reduced to
14 micro ampere level. All DACs and the internal PLL
16 - adi,power-mode-pll-ctrl: PLL and oversampling control. This control allows
17 internal PLL 1 circuit to be powered down and the
19 - ad,adv7343-power-mode-dac: array configuring the power on/off DAC's 1..6,
22 - ad,adv7343-sd-config-dac-out: array configure SD DAC Output's 1 and 2, 0 = OFF
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| /freebsd/contrib/ntp/kernel/sys/ |
| H A D | timex.h | 7 * that the above copyright notice appears in all copies and that both the *
8 * copyright notice and this permission notice appear in supporting *
9 * documentation, and that the name University of Delaware not be used in *
21 * Added defines for hybrid phase/frequency-lock loop.
25 * defines for PPS phase-lock loop.
45 * ntp_gettime - NTP user application interface
52 * int SYS_ntp_gettime defined in syscall.h header file
56 * ntp_adjtime - NTP daemon application interface
63 * int SYS_ntp_adjtime defined in syscall.h header file
76 * phase-lock loop (PLL) model used in the kernel implementation. These
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| /freebsd/sys/contrib/device-tree/Bindings/display/ti/ |
| H A D | ti,dra7-dss.txt | 4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
8 --------
11 - compatible: "ti,dra7-dss"
12 - reg: address and length of the register spaces for 'dss'
13 - ti,hwmods: "dss_core"
14 - clocks: handle to fclk
15 - clock-names: "fck"
16 - syscon: phandle to control module core syscon node
20 Some DRA7xx SoCs have one dedicated video PLL, some have two. These properties
23 - reg: address and length of the register spaces for 'pll1_clkctrl',
[all …]
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