| /linux/drivers/gpu/drm/ |
| H A D | drm_plane.c | 42 * A plane represents an image source that can be blended with or overlaid on
44 * &drm_framebuffer object. The plane itself specifies the cropping and scaling
46 * pipeline, represented by &drm_crtc. A plane can also have additional
52 * which are not covered by a plane will be black, and alpha blending of any
55 * To create a plane, a KMS drivers allocates and zeroes an instances of
59 * Each plane has a type, see enum drm_plane_type. A plane can be compatible
62 * Each CRTC must have a unique primary plane userspace can attach to enable
64 * primary plane to each CRTC at the same time. Primary planes can still be
69 * relies on the driver to set the primary and optionally the cursor plane used
71 * drivers must provide one primary plane per CRTC to avoid surprising legacy
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| H A D | drm_plane_helper.c | 4 * DRM universal plane helper functions
44 * This helper library contains helpers to implement primary plane support on
47 * plane together with the CRTC state this does not allow userspace to disable
48 * the primary plane itself. The default primary plane only expose XRBG8888 and
55 * The plane helpers share the function table structures with other helpers,
75 * Note: Once we change the plane hooks to more fine-grained locking we in get_connectors_for_crtc()
95 static int drm_plane_helper_check_update(struct drm_plane *plane, in drm_plane_helper_check_update() argument
108 .plane = plane, in drm_plane_helper_check_update()
144 * @plane: plane to update
145 * @crtc: the plane's new CRTC
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| /linux/drivers/gpu/drm/virtio/ |
| H A D | virtgpu_plane.c | 75 drm_plane_state *virtio_gpu_plane_duplicate_state(struct drm_plane *plane) in virtio_gpu_plane_duplicate_state() argument
79 if (WARN_ON(!plane->state)) in virtio_gpu_plane_duplicate_state()
86 __drm_atomic_helper_plane_duplicate_state(plane, &new->base); in virtio_gpu_plane_duplicate_state()
99 static int virtio_gpu_plane_atomic_check(struct drm_plane *plane, in virtio_gpu_plane_atomic_check() argument
103 plane); in virtio_gpu_plane_atomic_check()
105 plane); in virtio_gpu_plane_atomic_check()
106 bool is_cursor = plane->type == DRM_PLANE_TYPE_CURSOR; in virtio_gpu_plane_atomic_check()
114 * Ignore damage clips if the framebuffer attached to the plane's state in virtio_gpu_plane_atomic_check()
115 * has changed since the last plane update (page-flip). In this case, a in virtio_gpu_plane_atomic_check()
116 * full plane update should happen because uploads are done per-buffer. in virtio_gpu_plane_atomic_check()
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| /linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_plane.c | 25 * DOC: atomic plane helpers
27 * The functions here are used by the atomic plane helper functions to
28 * implement legacy plane updates (i.e., drm_plane->update_plane() and
29 * drm_plane->disable_plane()). This allows plane updates to use the
30 * atomic state infrastructure and perform plane updates as separate
66 struct intel_plane *plane) in intel_plane_state_reset() argument
70 __drm_atomic_helper_plane_state_reset(&plane_state->uapi, &plane->base); in intel_plane_state_reset()
78 struct intel_plane *plane; in intel_plane_alloc() local
80 plane = kzalloc_obj(*plane); in intel_plane_alloc()
81 if (!plane) in intel_plane_alloc()
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| H A D | skl_universal_plane_regs.h | 11 #define _SKL_PLANE(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \ argument
12 _PLANE((plane), _PIPE((pipe), (reg_1_a), (reg_1_b)), _PIPE((pipe), (reg_2_a), (reg_2_b)))
13 #define _SKL_PLANE_DW(pipe, plane, dw, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \ argument
14 (_SKL_PLANE((pipe), (plane), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b)) + (dw) * 4)
15 #define _MMIO_SKL_PLANE(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \ argument
16 _MMIO(_SKL_PLANE((pipe), (plane), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b)))
17 #define _MMIO_SKL_PLANE_DW(pipe, plane, dw, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \ argument
18 _MMIO(_SKL_PLANE_DW((pipe), (plane), (dw), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b)))
20 #define _SEL_FETCH(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b, reg_5_a, reg_5_b, reg_6_a, reg_… argument
21 _PICK_EVEN_2RANGES((plane), PLANE_5, \
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| H A D | i9xx_plane_regs.h | 12 #define DSPADDR_VLV(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV) argument
15 #define DSPCNTR(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPACNTR) argument
41 #define DISP_ALPHA_TRANS_ENABLE REG_BIT(15) /* pre-g4x plane B */
46 #define DISP_SPRITE_ABOVE_OVERLAY REG_BIT(0) /* pre-g4x plane B/C */
49 #define DSPADDR(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR) argument
52 #define DSPLINOFF(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPALINOFF) argument
55 #define DSPSTRIDE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE) argument
58 #define DSPPOS(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAPOS) argument
65 #define DSPSIZE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE) argument
72 #define DSPSURF(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURF) argument
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| /linux/drivers/gpu/drm/nouveau/dispnv04/ |
| H A D | overlay.c | 113 nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, in nv10_update_plane() argument
120 struct nouveau_drm *drm = nouveau_drm(plane->dev); in nv10_update_plane()
123 container_of(plane, struct nouveau_plane, base); in nv10_update_plane()
192 nv10_disable_plane(struct drm_plane *plane, in nv10_disable_plane() argument
195 struct nvif_object *dev = &nouveau_drm(plane->dev)->client.device.object; in nv10_disable_plane()
197 container_of(plane, struct nouveau_plane, base); in nv10_disable_plane()
209 nv_destroy_plane(struct drm_plane *plane) in nv_destroy_plane() argument
211 drm_plane_force_disable(plane); in nv_destroy_plane()
212 drm_plane_cleanup(plane); in nv_destroy_plane()
213 kfree(plane); in nv_destroy_plane()
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| /linux/include/drm/ |
| H A D | drm_plane.h | 46 * struct drm_plane_state - mutable plane state
55 /** @plane: backpointer to the plane */
56 struct drm_plane *plane; member
90 * Left position of visible portion of plane on crtc, signed dest
98 * Upper position of visible portion of plane on crtc, signed dest
103 /** @crtc_w: width of visible portion of plane on crtc */
104 /** @crtc_h: height of visible portion of plane on crtc */
108 * @src_x: left position of visible portion of plane within plane (in
113 * @src_y: upper position of visible portion of plane within plane (in
117 /** @src_w: width of visible portion of plane (in 16.16) */
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| /linux/drivers/gpu/drm/mediatek/ |
| H A D | mtk_plane.c | 28 static void mtk_plane_reset(struct drm_plane *plane) in mtk_plane_reset() argument
32 if (plane->state) { in mtk_plane_reset()
33 __drm_atomic_helper_plane_destroy_state(plane->state); in mtk_plane_reset()
35 state = to_mtk_plane_state(plane->state); in mtk_plane_reset()
43 __drm_atomic_helper_plane_reset(plane, &state->base); in mtk_plane_reset()
45 state->base.plane = plane; in mtk_plane_reset()
50 static struct drm_plane_state *mtk_plane_duplicate_state(struct drm_plane *plane) in mtk_plane_duplicate_state() argument
52 struct mtk_plane_state *old_state = to_mtk_plane_state(plane->state); in mtk_plane_duplicate_state()
59 __drm_atomic_helper_plane_duplicate_state(plane, &state->base); in mtk_plane_duplicate_state()
61 WARN_ON(state->base.plane != plane); in mtk_plane_duplicate_state()
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| /linux/drivers/gpu/drm/omapdrm/ |
| H A D | omap_plane.c | 19 * plane funcs
46 static int omap_plane_prepare_fb(struct drm_plane *plane, in omap_plane_prepare_fb() argument
52 drm_gem_plane_helper_prepare_fb(plane, new_state); in omap_plane_prepare_fb()
57 static void omap_plane_cleanup_fb(struct drm_plane *plane, in omap_plane_cleanup_fb() argument
64 static void omap_plane_atomic_update(struct drm_plane *plane, in omap_plane_atomic_update() argument
67 struct omap_drm_private *priv = plane->dev->dev_private; in omap_plane_atomic_update()
69 plane); in omap_plane_atomic_update()
71 plane); in omap_plane_atomic_update()
91 DBG("[PLANE:%d:%s] no overlay attached", plane->base.id, plane->name); in omap_plane_atomic_update()
96 DBG("%s, crtc=%p fb=%p", plane->name, new_state->crtc, in omap_plane_atomic_update()
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| /linux/drivers/gpu/drm/renesas/rcar-du/ |
| H A D | rcar_du_plane.c | 27 * Atomic hardware plane allocator
29 * The hardware plane allocator is solely based on the atomic plane states
35 * the allocated hardware plane(s) for each KMS plane. The allocator then loops
36 * over all plane states to compute the free planes bitmask, allocates hardware
37 * planes based on that bitmask, and stores the result back in the plane states.
56 * as the extra hardware plane will be freed when committing, but doing in rcar_du_plane_needs_realloc()
86 * VSPD1. VSPD0 feeds DU0/1 plane 0, and VSPD1 feeds either DU2 plane 0 or
87 * DU0/1 plane 1.
89 * Allocate the correct fixed plane when sourcing frames from VSPD0 or VSPD1,
96 static int rcar_du_plane_hwalloc(struct rcar_du_plane *plane, in rcar_du_plane_hwalloc() argument
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| /linux/drivers/gpu/drm/renesas/rz-du/ |
| H A D | rzg2l_du_vsp.c | 77 struct drm_plane *plane = NULL; in rzg2l_du_vsp_get_drm_plane() local
79 drm_for_each_plane(plane, &rcdu->ddev) { in rzg2l_du_vsp_get_drm_plane()
80 struct rzg2l_du_vsp_plane *vsp_plane = to_rzg2l_vsp_plane(plane); in rzg2l_du_vsp_get_drm_plane()
86 return plane ? plane : ERR_PTR(-EINVAL); in rzg2l_du_vsp_get_drm_plane()
117 static void rzg2l_du_vsp_plane_setup(struct rzg2l_du_vsp_plane *plane) in rzg2l_du_vsp_plane_setup() argument
120 to_rzg2l_vsp_plane_state(plane->plane.state); in rzg2l_du_vsp_plane_setup()
122 struct drm_framebuffer *fb = plane->plane.state->fb; in rzg2l_du_vsp_plane_setup()
171 vsp1_du_atomic_update(plane->vsp->vsp, crtc->vsp_pipe, in rzg2l_du_vsp_plane_setup()
172 plane->index, &cfg); in rzg2l_du_vsp_plane_setup()
175 static int __rzg2l_du_vsp_plane_atomic_check(struct drm_plane *plane, in __rzg2l_du_vsp_plane_atomic_check() argument
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| /linux/drivers/gpu/drm/atmel-hlcdc/ |
| H A D | atmel_hlcdc_plane.c | 24 * struct atmel_hlcdc_plane_state - Atmel HLCDC Plane state structure.
26 * @base: DRM plane state
27 * @crtc_x: x position of the plane relative to the CRTC
28 * @crtc_y: y position of the plane relative to the CRTC
29 * @crtc_w: visible width of the plane
30 * @crtc_h: visible height of the plane
273 atmel_hlcdc_plane_scaler_set_phicoeff(struct atmel_hlcdc_plane *plane, in atmel_hlcdc_plane_scaler_set_phicoeff() argument
280 atmel_hlcdc_layer_write_cfg(&plane->layer, cfg_offs + i, in atmel_hlcdc_plane_scaler_set_phicoeff()
285 void atmel_hlcdc_plane_setup_scaler(struct atmel_hlcdc_plane *plane, in atmel_hlcdc_plane_setup_scaler() argument
288 const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; in atmel_hlcdc_plane_setup_scaler()
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| /linux/drivers/gpu/drm/arm/display/komeda/ |
| H A D | komeda_plane.c | 20 struct komeda_plane *kplane = to_kplane(st->plane); in komeda_plane_init_data_flow()
32 st->plane->name, st->normalized_zpos, in komeda_plane_init_data_flow()
64 * @plane: DRM plane
65 * @state: the plane state object
71 komeda_plane_atomic_check(struct drm_plane *plane, in komeda_plane_atomic_check() argument
75 plane); in komeda_plane_atomic_check()
76 struct komeda_plane *kplane = to_kplane(plane); in komeda_plane_atomic_check()
90 DRM_DEBUG_ATOMIC("Cannot update plane on a disabled CRTC.\n"); in komeda_plane_atomic_check()
114 /* plane doesn't represent a real HW, so there is no HW update for plane.
118 komeda_plane_atomic_update(struct drm_plane *plane, in komeda_plane_atomic_update() argument
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| /linux/drivers/gpu/drm/omapdrm/dss/ |
| H A D | dispc.h | 342 static inline u16 DISPC_OVL_BASE(enum omap_plane_id plane) in DISPC_OVL_BASE() argument
344 switch (plane) { in DISPC_OVL_BASE()
362 static inline u16 DISPC_BA0_OFFSET(enum omap_plane_id plane) in DISPC_BA0_OFFSET() argument
364 switch (plane) { in DISPC_BA0_OFFSET()
378 static inline u16 DISPC_BA1_OFFSET(enum omap_plane_id plane) in DISPC_BA1_OFFSET() argument
380 switch (plane) { in DISPC_BA1_OFFSET()
394 static inline u16 DISPC_BA0_UV_OFFSET(enum omap_plane_id plane) in DISPC_BA0_UV_OFFSET() argument
396 switch (plane) { in DISPC_BA0_UV_OFFSET()
414 static inline u16 DISPC_BA1_UV_OFFSET(enum omap_plane_id plane) in DISPC_BA1_UV_OFFSET() argument
416 switch (plane) { in DISPC_BA1_UV_OFFSET()
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| /linux/drivers/video/fbdev/omap2/omapfb/dss/ |
| H A D | dispc.h | 339 static inline u16 DISPC_OVL_BASE(enum omap_plane plane) in DISPC_OVL_BASE() argument
341 switch (plane) { in DISPC_OVL_BASE()
359 static inline u16 DISPC_BA0_OFFSET(enum omap_plane plane) in DISPC_BA0_OFFSET() argument
361 switch (plane) { in DISPC_BA0_OFFSET()
375 static inline u16 DISPC_BA1_OFFSET(enum omap_plane plane) in DISPC_BA1_OFFSET() argument
377 switch (plane) { in DISPC_BA1_OFFSET()
391 static inline u16 DISPC_BA0_UV_OFFSET(enum omap_plane plane) in DISPC_BA0_UV_OFFSET() argument
393 switch (plane) { in DISPC_BA0_UV_OFFSET()
411 static inline u16 DISPC_BA1_UV_OFFSET(enum omap_plane plane) in DISPC_BA1_UV_OFFSET() argument
413 switch (plane) { in DISPC_BA1_UV_OFFSET()
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| /linux/drivers/gpu/drm/tegra/ |
| H A D | plane.c | 17 #include "plane.h"
19 static void tegra_plane_destroy(struct drm_plane *plane) in tegra_plane_destroy() argument
21 struct tegra_plane *p = to_tegra_plane(plane); in tegra_plane_destroy()
23 drm_plane_cleanup(plane); in tegra_plane_destroy()
27 static void tegra_plane_reset(struct drm_plane *plane) in tegra_plane_reset() argument
29 struct tegra_plane *p = to_tegra_plane(plane); in tegra_plane_reset()
33 if (plane->state) in tegra_plane_reset()
34 __drm_atomic_helper_plane_destroy_state(plane->state); in tegra_plane_reset()
36 kfree(plane->state); in tegra_plane_reset()
37 plane->state = NULL; in tegra_plane_reset()
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| H A D | dc.c | 37 #include "plane.h"
62 static inline unsigned int tegra_plane_offset(struct tegra_plane *plane, in tegra_plane_offset() argument
67 return plane->offset + offset; in tegra_plane_offset()
72 return plane->offset + offset; in tegra_plane_offset()
77 return plane->offset + offset; in tegra_plane_offset()
80 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset); in tegra_plane_offset()
82 return plane->offset + offset; in tegra_plane_offset()
85 static inline u32 tegra_plane_readl(struct tegra_plane *plane, in tegra_plane_readl() argument
88 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset)); in tegra_plane_readl()
91 static inline void tegra_plane_writel(struct tegra_plane *plane, u32 value, in tegra_plane_writel() argument
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| /linux/drivers/gpu/drm/sun4i/ |
| H A D | sun4i_layer.c | 19 static void sun4i_backend_layer_reset(struct drm_plane *plane) in sun4i_backend_layer_reset() argument
23 if (plane->state) { in sun4i_backend_layer_reset()
24 state = state_to_sun4i_layer_state(plane->state); in sun4i_backend_layer_reset()
29 plane->state = NULL; in sun4i_backend_layer_reset()
34 __drm_atomic_helper_plane_reset(plane, &state->state); in sun4i_backend_layer_reset()
38 sun4i_backend_layer_duplicate_state(struct drm_plane *plane) in sun4i_backend_layer_duplicate_state() argument
40 struct sun4i_layer_state *orig = state_to_sun4i_layer_state(plane->state); in sun4i_backend_layer_duplicate_state()
47 __drm_atomic_helper_plane_duplicate_state(plane, ©->state); in sun4i_backend_layer_duplicate_state()
53 static void sun4i_backend_layer_destroy_state(struct drm_plane *plane, in sun4i_backend_layer_destroy_state() argument
63 static void sun4i_backend_layer_atomic_disable(struct drm_plane *plane, in sun4i_backend_layer_atomic_disable() argument
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| /linux/Documentation/gpu/ |
| H A D | afbc.rst | 87 Within each plane, the component ordering also follows the fourcc
94 * Plane 0:
102 * Plane 0:
106 * Plane 1:
127 - Plane 0: 4 components
135 - Plane 0: 4 components
143 - Plane 0: 3 components
150 - Plane 0: 3 components
157 - Plane 0: 4 components
164 - 8-bit per component YCbCr 444, single plane
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| /linux/drivers/gpu/drm/msm/disp/mdp5/ |
| H A D | mdp5_plane.c | 23 static int mdp5_plane_mode_set(struct drm_plane *plane,
27 static struct mdp5_kms *get_kms(struct drm_plane *plane) in get_kms() argument
29 struct msm_drm_private *priv = plane->dev->dev_private; in get_kms()
39 static void mdp5_plane_install_properties(struct drm_plane *plane, in mdp5_plane_install_properties() argument
44 drm_plane_create_rotation_property(plane, in mdp5_plane_install_properties()
50 drm_plane_create_alpha_property(plane); in mdp5_plane_install_properties()
51 drm_plane_create_blend_mode_property(plane, in mdp5_plane_install_properties()
56 if (plane->type == DRM_PLANE_TYPE_PRIMARY) in mdp5_plane_install_properties()
59 zpos = STAGE0 + drm_plane_index(plane); in mdp5_plane_install_properties()
60 drm_plane_create_zpos_property(plane, zpos, 1, 255); in mdp5_plane_install_properties()
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| /linux/Documentation/gpu/amdgpu/display/ |
| H A D | mpo-overview.rst | 17 * Plane independent page flips - No need to be tied to global compositor
31 * ``DRM_PLANE_TYPE_PRIMARY``: Primary planes represent a "main" plane for a
34 * ``DRM_PLANE_TYPE_CURSOR``: Cursor planes represent a "cursor" plane for a
45 * 1 Overlay plane (shared among CRTCs).
53 configuration for optimal single display output (e.g., 2 pipes per plane).
56 display - will see 4 pipes in use, 2 per plane.
58 At least 1 pipe must be used per plane (primary and overlay), so for this
65 Plane Restrictions
78 Not every property is available on every plane:
94 plane as it is being treated as part of the plane. Another consequence of that
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| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_plane.c | 47 * plane capabilities, or initialize this array to all formats, so internal drm
394 /* TODO: This seems wrong because there is no DCC plane on GFX12. */ in amdgpu_dm_plane_fill_gfx12_plane_attributes_from_modifiers()
781 static int amdgpu_dm_plane_get_plane_formats(const struct drm_plane *plane, in amdgpu_dm_plane_get_plane_formats() argument
789 * DC plane caps. This will require adding more formats to the in amdgpu_dm_plane_get_plane_formats()
793 if (plane->type == DRM_PLANE_TYPE_PRIMARY || in amdgpu_dm_plane_get_plane_formats()
794 …(plane_cap && plane_cap->type == DC_PLANE_TYPE_DCN_UNIVERSAL && plane->type != DRM_PLANE_TYPE_CURS… in amdgpu_dm_plane_get_plane_formats()
813 switch (plane->type) { in amdgpu_dm_plane_get_plane_formats()
926 static int amdgpu_dm_plane_helper_prepare_fb(struct drm_plane *plane, in amdgpu_dm_plane_helper_prepare_fb() argument
961 if (plane->type != DRM_PLANE_TYPE_CURSOR) in amdgpu_dm_plane_helper_prepare_fb()
980 r = drm_gem_plane_helper_prepare_fb(plane, new_state); in amdgpu_dm_plane_helper_prepare_fb()
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| /linux/drivers/gpu/drm/tidss/ |
| H A D | tidss_plane.c | 21 void tidss_plane_error_irq(struct drm_plane *plane, u64 irqstatus) in tidss_plane_error_irq() argument
23 struct tidss_plane *tplane = to_tidss_plane(plane); in tidss_plane_error_irq()
25 dev_err_ratelimited(plane->dev->dev, "Plane%u underflow (irq %llx)\n", in tidss_plane_error_irq()
31 static int tidss_plane_atomic_check(struct drm_plane *plane, in tidss_plane_atomic_check() argument
35 plane); in tidss_plane_atomic_check()
36 struct drm_device *ddev = plane->dev; in tidss_plane_atomic_check()
38 struct tidss_plane *tplane = to_tidss_plane(plane); in tidss_plane_atomic_check()
115 static void tidss_plane_atomic_update(struct drm_plane *plane, in tidss_plane_atomic_update() argument
118 struct drm_device *ddev = plane->dev; in tidss_plane_atomic_update()
120 struct tidss_plane *tplane = to_tidss_plane(plane); in tidss_plane_atomic_update()
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| /linux/drivers/gpu/drm/vkms/ |
| H A D | vkms_plane.c | 54 vkms_plane_duplicate_state(struct drm_plane *plane) in vkms_plane_duplicate_state() argument
72 __drm_gem_duplicate_shadow_plane_state(plane, &vkms_state->base); in vkms_plane_duplicate_state()
77 static void vkms_plane_destroy_state(struct drm_plane *plane, in vkms_plane_destroy_state() argument
98 static void vkms_plane_reset(struct drm_plane *plane) in vkms_plane_reset() argument
102 if (plane->state) { in vkms_plane_reset()
103 vkms_plane_destroy_state(plane, plane->state); in vkms_plane_reset()
104 plane->state = NULL; /* must be set to NULL here */ in vkms_plane_reset()
113 __drm_gem_reset_shadow_plane(plane, &vkms_state->base); in vkms_plane_reset()
124 static void vkms_plane_atomic_update(struct drm_plane *plane, in vkms_plane_atomic_update() argument
128 plane); in vkms_plane_atomic_update()
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