Home
last modified time | relevance | path

Searched +full:phy +full:- +full:reset +full:- +full:post +full:- +full:delay (Results 1 – 25 of 107) sorted by relevance

12345

/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dfsl-fec.txt4 - compatible : Should be "fsl,<soc>-fec"
5 - reg : Address and length of the register set for the device
6 - interrupts : Should contain fec interrupt
7 - phy-mode : See ethernet.txt file in the same directory
10 - phy-supply : regulator that powers the Ethernet PHY.
11 - phy-handle : phandle to the PHY device connected to this device.
12 - fixed-link : Assume a fixed link. See fixed-link.txt in the same directory.
13 Use instead of phy-handle.
14 - fsl,num-tx-queues : The property is valid for enet-avb IP, which supports
17 - fsl,num-rx-queues : The property is valid for enet-avb IP, which supports
[all …]
H A Dfsl,fec.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Wei Fang <wei.fang@nxp.com>
12 - NXP Linux Team <linux-imx@nxp.com>
15 - $ref: ethernet-controller.yaml#
20 - enum:
21 - fsl,imx25-fec
22 - fsl,imx27-fec
[all …]
H A Dmdio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
17 bus. These should follow the generic ethernet-phy.yaml document, or
22 pattern: '^mdio(-(bus|external))?(@.+|-([0-9]+))?$'
24 "#address-cells":
27 "#size-cells":
[all …]
H A Dhisilicon-femac.txt4 - compatible: should contain one of the following version strings:
5 * "hisilicon,hisi-femac-v1"
6 * "hisilicon,hisi-femac-v2"
7 and the soc string "hisilicon,hi3516cv300-femac".
8 - reg: specifies base physical address(s) and size of the device registers.
11 - interrupts: should contain the MAC interrupt.
12 - clocks: A phandle to the MAC main clock.
13 - resets: should contain the phandle to the MAC reset signal(required) and
14 the PHY reset signal(optional).
15 - reset-names: should contain the reset signal name "mac"(required)
[all …]
H A Dhisilicon-hix5hd2-gmac.txt4 - compatible: should contain one of the following SoC strings:
5 * "hisilicon,hix5hd2-gmac"
6 * "hisilicon,hi3798cv200-gmac"
7 * "hisilicon,hi3516a-gmac"
9 * "hisilicon,hisi-gmac-v1"
10 * "hisilicon,hisi-gmac-v2"
13 - reg: specifies base physical address(s) and size of the device registers.
16 - interrupts: should contain the MAC interrupt.
17 - #address-cells: must be <1>.
18 - #size-cells: must be <0>.
[all …]
H A Drenesas,ethertsn.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Ethernet TSN End-station
10 - Niklas Söderlund <niklas.soderlund@ragnatech.se>
14 Gbps full-duplex link via MII/GMII/RMII/RGMII. Depending on the connected PHY.
17 - $ref: ethernet-controller.yaml#
22 - enum:
23 - renesas,r8a779g0-ethertsn # R-Car V4H
24 - const: renesas,rcar-gen4-ethertsn
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/renesas/
H A Dwhite-hawk-ethernet.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the White Hawk RAVB/Ethernet(1000Base-T1)
4 * sub-board
17 pinctrl-0 = <&avb1_pins>;
18 pinctrl-names = "default";
19 phy-handle = <&avb1_phy>;
23 #address-cells = <1>;
24 #size-cells = <0>;
26 reset-gpios = <&gpio6 1 GPIO_ACTIVE_LOW>;
27 reset-post-delay-us = <4000>;
[all …]
H A Dr8a779g2-white-hawk-single.dts1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the R-Car V4H ES2.0 White Hawk Single board
8 /dts-v1/;
10 #include "white-hawk-cpu-common.dtsi"
11 #include "white-hawk-common.dtsi"
15 compatible = "renesas,white-hawk-single", "renesas,r8a779g2",
20 uart-has-rtscts;
38 bias-disable;
43 drive-strength = <24>;
44 bias-disable;
[all …]
H A Dbeacon-renesom-som.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/clock/versaclock.h>
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
19 clock-frequency = <32768>;
20 clock-output-names = "osc_32k";
23 reg_1p8v: regulator-1p8v {
24 compatible = "regulator-fixed";
25 regulator-name = "fixed-1.8V";
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dmba6ulx.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright 2018-2022 TQ-Systems GmbH
4 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
8 model = "TQ-Systems MBA6ULx Baseboard";
18 stdout-path = &uart1;
22 compatible = "pwm-backlight";
23 power-supply = <&reg_mba6ul_3v3>;
24 enable-gpios = <&expander_out0 4 GPIO_ACTIVE_HIGH>;
29 compatible = "gpio-beeper";
33 gpio_buttons: gpio-keys {
[all …]
H A Dimx6qdl-apf6.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
9 reg_1p8v: regulator-1p8v {
10 compatible = "regulator-fixed";
11 regulator-name = "1P8V";
12 regulator-min-microvolt = <1800000>;
13 regulator-max-microvolt = <1800000>;
14 regulator-always-on;
15 vin-supply = <&reg_3p3v>;
[all …]
H A Dimx7d-flex-concentrator.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
11 #include "imx7d-tqma7.dtsi"
14 /delete-node/ &ds1339;
18 compatible = "kam,imx7d-flex-concentrator", "fsl,imx7d";
22 /* 1024 MB - TQMa7D board configuration */
26 reg_usb_otg2_vbus: regulator-us
[all...]
/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt7986a-acelink-ew-7886cax.dts1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/leds/common.h>
11 compatible = "acelink,ew-7886cax", "mediatek,mt7986a";
12 model = "Acelink EW-7886CAX";
19 stdout-path = "serial0:115200n8";
28 compatible = "gpio-keys";
30 key-restart {
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx93-var-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
12 model = "Variscite VAR-SOM-MX93 module";
13 compatible = "variscite,var-som-mx93", "fsl,imx93";
15 mmc_pwrseq: mmc-pwrseq {
16 compatible = "mmc-pwrseq-simple";
17 post-power-on-delay-ms = <100>;
18 power-off-delay-us = <10000>;
19 reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */
23 reg_eqos_phy: regulator-eqos-phy {
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/allwinner/
H A Dsun50i-h5-nanopi-r1s-h5.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Based on sun50i-h5-nanopi-neo-plus2.dts, which is:
10 /dts-v1/;
11 #include "sun50i-h5.dtsi"
12 #include "sun50i-h5-cpu-opp.dtsi"
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/leds/common.h>
20 compatible = "friendlyarm,nanopi-r1s-h5", "allwinner,sun50i-h5";
29 stdout-path = "serial0:115200n8";
[all …]
H A Dsun50i-h5-nanopi-neo-plus2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 /dts-v1/;
6 #include "sun50i-h5.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/pinctrl/sun4i-a10.h>
14 compatible = "friendlyarm,nanopi-neo-plus2", "allwinner,sun50i-h5";
22 stdout-path = "serial0:115200n8";
26 compatible = "gpio-leds";
28 led-0 {
[all …]
/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dstm32mp15xx-dhcor-testbench.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
17 stdout-path = "serial0:115200n8";
20 sd_switch: regulator-sd_switch {
21 compatible = "regulator-gpio";
22 regulator-name = "sd_switch";
23 regulator-mi
[all...]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-j7200-evm-quad-port-eth-exp.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * DT Overlay for CPSW5G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with
6 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
9 /dts-v1/;
12 #include <dt-bindings/gpio/gpio.h>
14 #include "k3-pinctrl.h"
15 #include "k3-serdes.h"
19 ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
20 ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
21 ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3";
[all …]
H A Dk3-j721e-evm-quad-port-eth-exp.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with
6 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
9 /dts-v1/;
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/phy/phy-cadence.h>
16 #include "k3-pinctrl.h"
17 #include "k3-serdes.h"
21 ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
[all …]
H A Dk3-j784s4-evm-quad-port-eth-exp1.dtso1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
3 * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with
4 * J784S4 EVM. The Add-On Ethernet Card has to be connected to ENET Expansion 1 slot on the
11 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
14 /dts-v1/;
17 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/phy/phy-cadence.h>
19 #include <dt-bindings/phy/phy.h>
21 #include "k3-pinctrl.h"
22 #include "k3-serdes.h"
[all …]
/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Ddwc3.txt3 DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties
7 - compatible: must be "snps,dwc3"
8 - reg : Address and length of the register set for the device
9 - interrupts: Interrupts used by the dwc3 controller.
10 - clock-names: list of clock names. Ideally should be "ref",
12 - clocks: list of phandle and clock specifier pairs corresponding to
13 entries in the clock-names property.
16 clocks are optional if the parent node (i.e. glue-layer) is compatible to
18 "cavium,octeon-7130-usb-uctl"
20 "samsung,exynos5250-dwusb3"
[all …]
/freebsd/sys/dev/etherswitch/ar40xx/
H A Dar40xx_hw_psgmii.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
76 * Routines that control the ess-psgmii block - the interconnect
77 * between the ess-switch and the external multi-port PHY
85 bus_space_write_4(sc->sc_psgmii_mem_tag, sc->sc_psgmii_mem_handle, in ar40xx_hw_psgmii_reg_write()
87 bus_space_barrier(sc->sc_psgmii_mem_tag, sc->sc_psgmii_mem_handle, in ar40xx_hw_psgmii_reg_write()
88 0, sc->sc_psgmii_mem_size, BUS_SPACE_BARRIER_WRITE); in ar40xx_hw_psgmii_reg_write()
96 bus_space_barrier(sc->sc_psgmii_mem_tag, sc->sc_psgmii_mem_handle, in ar40xx_hw_psgmii_reg_read()
97 0, sc->sc_psgmii_mem_size, BUS_SPACE_BARRIER_READ); in ar40xx_hw_psgmii_reg_read()
98 ret = bus_space_read_4(sc->sc_psgmii_mem_tag, sc->sc_psgmii_mem_handle, in ar40xx_hw_psgmii_reg_read()
[all …]
/freebsd/sys/contrib/device-tree/src/mips/ingenic/
H A Dcu1000-neo.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/clock/ingenic,sysost.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
10 compatible = "yna,cu1000-neo", "ingenic,x1000e";
11 model = "YSH & ATIL General Board CU1000-Neo";
18 stdout-path = "serial2:115200n8";
27 compatible = "gpio-leds";
28 led-0 {
[all …]
H A Dcu1830-neo.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/clock/ingenic,sysost.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
10 compatible = "yna,cu1830-neo", "ingenic,x1830";
11 model = "YSH & ATIL General Board CU1830-Neo";
18 stdout-path = "serial1:115200n8";
27 compatible = "gpio-leds";
28 led-0 {
[all …]
/freebsd/sys/contrib/device-tree/src/arm/actions/
H A Dowl-s500-roseapplepi.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright (C) 2020-2021 Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
8 /dts-v1/;
10 #include "owl-s500.dtsi"
22 stdout-path = "serial2:115200n8";
30 syspwr: regulator-5v0 {
31 compatible = "regulator-fixed";
32 regulator-name = "SYSPWR";
33 regulator-min-microvolt = <5000000>;
34 regulator-max-microvolt = <5000000>;
[all …]

12345