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/linux/drivers/clk/hisilicon/
H A Dclk-hisi-phase.c1 // SPDX-License-Identifier: GPL-2.0
5 * Simple HiSilicon phase clock implementation.
23 u8 shift; member
30 static int hisi_phase_regval_to_degrees(struct clk_hisi_phase *phase, in hisi_phase_regval_to_degrees() argument
35 for (i = 0; i < phase->phase_num; i++) in hisi_phase_regval_to_degrees()
36 if (phase->phase_regvals[i] == regval) in hisi_phase_regval_to_degrees()
37 return phase->phase_degrees[i]; in hisi_phase_regval_to_degrees()
39 return -EINVAL; in hisi_phase_regval_to_degrees()
44 struct clk_hisi_phase *phase = to_clk_hisi_phase(hw); in hisi_clk_get_phase() local
47 regval = readl(phase->reg); in hisi_clk_get_phase()
[all …]
/linux/drivers/clk/sunxi-ng/
H A Dccu_phase.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 #include <linux/clk-provider.h>
15 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_get_phase() local
22 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_get_phase()
23 delay = (reg >> phase->shift); in ccu_phase_get_phase()
24 delay &= (1 << phase->width) - 1; in ccu_phase_get_phase()
32 return -EINVAL; in ccu_phase_get_phase()
37 return -EINVAL; in ccu_phase_get_phase()
42 return -EINVAL; in ccu_phase_get_phase()
[all …]
/linux/Documentation/devicetree/bindings/spi/
H A Dsamsung,spi-peripheral-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/samsung,spi-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for Samsung S3C/S5P/Exynos SoC SPI controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 See spi-peripheral-props.yaml for more info.
16 controller-data:
21 samsung,spi-feedback-delay:
23 The sampling phase shift to be applied on the miso line (to account
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/linux/Documentation/devicetree/bindings/leds/backlight/
H A Dsky81452-backlight.txt1 SKY81452-backlight bindings
4 - compatible : Must be "skyworks,sky81452-backlight"
7 - name : Name of backlight device. Default is 'lcd-backlight'.
8 - gpios : GPIO to use to EN pin.
10 - led-sources : List of enabled channels from 0 to 5.
12 - skyworks,ignore-pwm : Ignore both PWM input
13 - skyworks,dpwm-mode : Enable DPWM dimming mode, otherwise Analog dimming.
14 - skyworks,phase-shift : Enable phase shift mode
15 - skyworks,short-detection-threshold-volt
17 - skyworks,current-limit-mA
[all …]
/linux/drivers/staging/iio/Documentation/
H A Dsysfs-bus-iio-dds4 Contact: linux-iio@vger.kernel.org
8 which allows for pin controlled FSK Frequency Shift Keying
15 Contact: linux-iio@vger.kernel.org
24 Contact: linux-iio@vger.kernel.org
34 Contact: linux-iio@vger.kernel.org
36 Stores phase into Y.
38 allows for pin controlled PSK Phase Shift Keying
40 control the desired phase Y which is added to the phase
45 Contact: linux-iio@vger.kernel.org
48 the desired value in rad. If shared across all phase registers
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/linux/Documentation/devicetree/bindings/mmc/
H A Dsynopsys-dw-mshc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
16 - altr,socfpga-dw-mshc
17 - img,pistachio-dw-mshc
18 - snps,dw-mshc
33 clock-names:
35 - const: biu
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/linux/drivers/gpu/drm/i915/selftests/
H A Di915_syncmap.c41 for (d = 0; d < depth - 1; d++) { in __sync_print()
42 if (last & BIT(depth - d - 1)) in __sync_print()
47 *sz -= len; in __sync_print()
49 len = scnprintf(buf, *sz, "%x-> ", idx); in __sync_print()
51 *sz -= len; in __sync_print()
55 len = scnprintf(buf, *sz, "0x%016llx", p->prefix << p->height << SHIFT); in __sync_print()
57 *sz -= len; in __sync_print()
58 X = (p->height + SHIFT) / 4; in __sync_print()
59 scnprintf(buf - X, *sz + X, "%*s", X, "XXXXXXXXXXXXXXXXX"); in __sync_print()
61 if (!p->height) { in __sync_print()
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/linux/Documentation/ABI/testing/
H A Dsysfs-bus-iio-frequency-admv10131 What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage0-altvoltage1_i_calibphase
3 Contact: linux-iio@vger.kernel.org
5 Read/write unscaled value for the Local Oscillatior path quadrature I phase shift.
7 What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage0-altvoltage1_q_calibphase
9 Contact: linux-iio@vger.kernel.org
11 Read/write unscaled value for the Local Oscillatior path quadrature Q phase shift.
15 Contact: linux-iio@vger.kernel.org
22 Contact: linux-iio@vger.kernel.org
28 Contact: linux-iio@vger.kernel.org
35 Contact: linux-iio@vger.kernel.org
/linux/arch/parisc/include/asm/
H A Dhash.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * HP-PA only implements integer multiply in the FPU. However, for
7 * integer multiplies by constant, it has a number of shift-and-add
8 * (but no shift-and-subtract, sigh!) instructions that a compiler
20 * PA7100 pairing rules. This is an in-order 2-way superscalar processor.
21 * Only one instruction in a pair may be a shift (by more than 3 bits),
22 * but other than that, simple ALU ops (including shift-and-add by up
25 * PA8xxx processors also dual-issue ALU instructions, although with
28 * This 6-step sequence was found by Yevgen Voronenko's implementation
36 * Phase 1: Compute a = (x << 19) + x, in __hash_32()
[all …]
/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_util.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
4 * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
15 #define REG_MASK(n) ((BIT(n)) - 1)
41 * struct dpu_hw_blk - opaque hardware block object
52 * @ clip: clip shift
58 * @ prec_shift: precision shift
59 * @ adjust_a: A-coefficients for mapping curve
60 * @ adjust_b: B-coefficients for mapping curve
61 * @ adjust_c: C-coefficients for mapping curve
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dmicrochip,sparx5-switch.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/microchip,sparx5-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Steen Hegelund <steen.hegelund@microchip.com>
11 - Lars Povlsen <lars.povlsen@microchip.com>
12 - Daniel Machon <daniel.machon@microchip.com>
15 The SparX-5 Enterprise Ethernet switch family provides a rich set of
16 Enterprise switching features such as advanced TCAM-based VLAN and
18 security through TCAM-based frame processing using versatile content
[all …]
/linux/Documentation/devicetree/bindings/clock/ti/
H A Dapll.txt4 register-mapped APLL with usually two selectable input clocks
5 (reference clock and bypass clock), with analog phase locked
11 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
15 - compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock"
16 - #clock-cells : from common clock binding; shall be set to 0.
17 - clocks : link phandles of parent clocks (clk-ref and clk-bypass)
18 - reg : address and length of the register set for controlling the APLL.
20 "control" - contains the control register offset
21 "idlest" - contains the idlest register offset
22 "autoidle" - contains the autoidle register offset (OMAP2 only)
[all …]
/linux/drivers/regulator/
H A Dpf8x00-regulator.c1 // SPDX-License-Identifier: GPL-2.0+
97 #define PF8X00_SW_BASE(i) (8 * (i - PF8X00_BUCK1) + PF8X00_SW1_CONFIG1)
106 #define PF8X00_LDO_BASE(i) (6 * (i - PF8X00_LDO1) + PF8X00_LDO1_CONFIG1)
202 regmap_update_bits(chip->regmap, reg, in swxilim_select()
211 struct pf8x00_chip *chip = config->driver_data; in handle_ilim_property()
215 if ((desc->id >= PF8X00_BUCK1) && (desc->id <= PF8X00_BUCK7)) { in handle_ilim_property()
216 ret = of_property_read_u32(np, "nxp,ilim-ma", &val); in handle_ilim_property()
218 dev_dbg(chip->dev, "unspecified ilim for BUCK%d, use value stored in OTP\n", in handle_ilim_property()
219 desc->id - PF8X00_LDO4); in handle_ilim_property()
223 dev_warn(chip->dev, "nxp,ilim-ma is deprecated, please use regulator-max-microamp\n"); in handle_ilim_property()
[all …]
H A Drtq2208-regulator.c1 // SPDX-License-Identifier: GPL-2.0+
110 (const struct rtq2208_regulator_desc *)rdev->desc; in rtq2208_set_mode()
111 unsigned int val, shift; in rtq2208_set_mode() local
121 return -EINVAL; in rtq2208_set_mode()
124 shift = ffs(rdesc->mode_mask) - 1; in rtq2208_set_mode()
125 return regmap_update_bits(rdev->regmap, rdesc->mode_reg, in rtq2208_set_mode()
126 rdesc->mode_mask, val << shift); in rtq2208_set_mode()
132 (const struct rtq2208_regulator_desc *)rdev->desc; in rtq2208_get_mode()
136 ret = regmap_read(rdev->regmap, rdesc->mode_reg, &mode_val); in rtq2208_get_mode()
140 return (mode_val & rdesc->mode_mask) ? REGULATOR_MODE_FAST : REGULATOR_MODE_NORMAL; in rtq2208_get_mode()
[all …]
/linux/drivers/clk/rockchip/
H A Dclk-inverter.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <linux/clk-provider.h>
16 int shift; member
30 val = readl(inv_clock->reg) >> inv_clock->shift; in rockchip_inv_get_phase()
43 pr_err("%s: unsupported phase %d for %s\n", in rockchip_inv_set_phase()
45 return -EINVAL; in rockchip_inv_set_phase()
48 if (inv_clock->flags & ROCKCHIP_INVERTER_HIWORD_MASK) { in rockchip_inv_set_phase()
49 writel(HIWORD_UPDATE(val, INVERTER_MASK, inv_clock->shift), in rockchip_inv_set_phase()
50 inv_clock->reg); in rockchip_inv_set_phase()
55 spin_lock_irqsave(inv_clock->lock, flags); in rockchip_inv_set_phase()
[all …]
/linux/Documentation/devicetree/bindings/regulator/
H A Dnxp,pf8x00-regulator.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/regulator/nxp,pf8x00-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jagan Teki <jagan@amarulasolutions.com>
11 - Troy Kisky <troy.kisky@boundarydevices.com>
16 linear and one vsnvs regulators. It has built-in one time programmable
22 - nxp,pf8100
23 - nxp,pf8121a
24 - nxp,pf8200
[all …]
/linux/arch/powerpc/crypto/
H A Dghashp10-ppc.pl2 # SPDX-License-Identifier: GPL-2.0
26 # version is ~2.1x slower than hardware-assisted AES-128-CTR, ~12x
27 # faster than "4-bit" integer-only compiler-generated 64-bit code.
30 $flavour=shift;
31 $output =shift;
48 ( $xlate="${dir}ppc-xlate.pl" and -f $xlate ) or
49 ( $xlate="${dir}../../perlasm/ppc-xlate.pl" and -f $xlate) or
50 die "can't locate ppc-xlate.pl";
79 le?vxor 5,5,6 # set a b-endian mask
82 vspltisb $xC2,-16 # 0xf0
[all …]
H A Dghashp8-ppc.pl2 # SPDX-License-Identifier: GPL-2.0
26 # version is ~2.1x slower than hardware-assisted AES-128-CTR, ~12x
27 # faster than "4-bit" integer-only compiler-generated 64-bit code.
30 $flavour=shift;
31 $output =shift;
48 ( $xlate="${dir}ppc-xlate.pl" and -f $xlate ) or
49 ( $xlate="${dir}../../perlasm/ppc-xlate.pl" and -f $xlate) or
50 die "can't locate ppc-xlate.pl";
77 le?vxor 5,5,6 # set a b-endian mask
80 vspltisb $xC2,-16 # 0xf0
[all …]
/linux/kernel/time/
H A Dntp.c1 // SPDX-License-Identifier: GPL-2.0
27 * struct ntp_data - Structure holding all NTP related state
41 * @ntp_tick_adj: Constant boot-param configurable NTP tick adjustment (upscaled)
45 * @pps_tf: PPS phase median filter
48 * @pps_shift: PPS current interval duration in seconds (shift value)
91 [ 0 ... TIMEKEEPERS_MAX - 1 ] = {
111 * The following variables are used when a pulse-per-second (PPS) signal
116 #define PPS_POPCORN 4 /* popcorn spike threshold (shift) */
117 #define PPS_INTMIN 2 /* min freq interval (s) (shift) */
118 #define PPS_INTMAX 8 /* max freq interval (s) (shift) */
[all …]
/linux/include/uapi/linux/
H A Dtimex.h28 * Added defines for hybrid phase/frequency-lock loop.
32 * defines for PPS phase-lock loop.
46 * 1995-08-13 Torsten Duwe
47 * kernel PLL updated to 1994-12-13 specs (rfc-1589)
48 * 1997-08-30 Ulrich Windl
50 * 2004-08-12 Christoph Lameter
62 * syscall interface - used (mainly by NTP daemon)
82 int shift; /* interval duration (s) (shift) (ro) */ member
121 int shift; /* interval duration (s) (shift) (ro) */ member
152 #define ADJ_OFFSET_SINGLESHOT 0x8001 /* old-fashioned adjtime */
[all …]
/linux/tools/testing/selftests/ptp/
H A Dtestptp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PTP 1588 clock support - User space test program
35 #define CLOCK_INVALID -1
113 return t->sec * NSEC_PER_SEC + t->nsec; in pctns()
120 " -c query the ptp clock's capabilities\n" in usage()
121 " -d name device to open\n" in usage()
122 " -e val read 'val' external time stamp events\n" in usage()
123 " -E val enable rising (1), falling (2), or both (3) edges\n" in usage()
124 " -f val adjust the ptp clock frequency by 'val' ppb\n" in usage()
125 " -F chan Enable single channel mask and keep device open for debugfs verification.\n" in usage()
[all …]
/linux/Documentation/devicetree/bindings/mfd/
H A Dsky81452.txt4 - compatible : Must be "skyworks,sky81452"
5 - reg : I2C slave address
8 - backlight : container node for backlight following the binding
9 in leds/backlight/sky81452-backlight.txt
10 - regulator : container node for regulators following the binding
11 in regulator/sky81452-regulator.txt
20 compatible = "skyworks,sky81452-backlight";
21 name = "pwm-backlight";
22 led-sources = <0 1 2 3 6>;
23 skyworks,ignore-pwm;
[all …]
/linux/arch/microblaze/include/asm/
H A Dhash.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 * multiply using shifts and adds. GCC can find a 9-step solution, but
12 * this 6-step solution was found by Yevgen Voronenko's implementation
17 * 6-shift, 6-add sequences for computing x * 0x61C88647. They are all
21 * return (a<<11) + (b<<6) + (c<<3) - b;
37 /* Phase 1: Compute three intermediate values */ in __hash_32()
43 /* Phase 2: Compute (a << 11) + (b << 6) + (c << 3) - b */ in __hash_32()
49 return a - b; /* (a << 11) + (b << 6) + (c << 3) - b */ in __hash_32()
56 * addition-subtraction chain. This one is not known to be in __hash_32()
57 * optimal, but at 37 steps, it's decent for a 31-bit multiplier. in __hash_32()
[all …]
/linux/include/uapi/linux/media/raspberrypi/
H A Dpisp_be_config.h1 /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
5 * Copyright (C) 2021 - Raspberry Pi Ltd
98 * struct pisp_be_global_config - PiSP global enable bitmaps
112 * struct pisp_be_input_buffer_config - PiSP Back End input buffer
121 * struct pisp_be_dpc_config - PiS
[all...]
/linux/drivers/input/joystick/iforce/
H A Diforce-ff.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2000-2002 Vojtech Pavlik <vojtech@ucw.cz>
4 * Copyright (c) 2001-2002, 2007 Johann Deneux <johann.deneux@gmail.com>
6 * USB/RS232 I-Force joysticks and wheels.
24 guard(mutex)(&iforce->mem_mutex); in make_magnitude_modifier()
26 if (allocate_resource(&iforce->device_memory, mod_chunk, 2, in make_magnitude_modifier()
27 iforce->device_memory.start, in make_magnitude_modifier()
28 iforce->device_memory.end, in make_magnitude_modifier()
30 return -ENOSPC; in make_magnitude_modifier()
33 data[0] = LO(mod_chunk->start); in make_magnitude_modifier()
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