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/linux/drivers/pinctrl/
H A Dpinctrl-single.c205 #define PCS_QUIRK_HAS_SHARED_IRQ (pcs->flags & PCS_QUIRK_SHARED_IRQ)
206 #define PCS_HAS_IRQ (pcs->flags & PCS_FEAT_IRQ)
207 #define PCS_HAS_PINCONF (pcs->flags & PCS_FEAT_PINCONF)
268 static unsigned int pcs_pin_reg_offset_get(struct pcs_device *pcs, in pcs_pin_reg_offset_get() argument
271 unsigned int mux_bytes = pcs->width / BITS_PER_BYTE; in pcs_pin_reg_offset_get()
273 if (pcs->bits_per_mux) { in pcs_pin_reg_offset_get()
276 pin_offset_bytes = (pcs->bits_per_pin * pin) / BITS_PER_BYTE; in pcs_pin_reg_offset_get()
283 static unsigned int pcs_pin_shift_reg_get(struct pcs_device *pcs, in pcs_pin_shift_reg_get() argument
286 return (pin % (pcs->width / pcs->bits_per_pin)) * pcs->bits_per_pin; in pcs_pin_shift_reg_get()
293 struct pcs_device *pcs; in pcs_pin_dbg_show() local
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1046-post.dtsi27 pcs-handle = <&qsgmiib_pcs3>;
28 pcs-handle-names = "qsgmii";
42 pcs-handle = <&pcsphy4>, <&qsgmiib_pcs1>;
43 pcs-handle-names = "sgmii", "qsgmii";
48 pcs-handle = <&pcsphy5>, <&pcsphy5>;
49 pcs-handle-names = "sgmii", "qsgmii";
57 pcs-handle = <&pcsphy7>, <&qsgmiib_pcs2>, <&pcsphy7>;
58 pcs-handle-names = "sgmii", "qsgmii", "xfi";
62 qsgmiib_pcs1: ethernet-pcs@1 {
63 compatible = "fsl,lynx-pcs";
[all …]
H A Dfsl-ls1043-post.dtsi27 pcs-handle-names = "qsgmii";
32 pcs-handle = <&pcsphy1>, <&qsgmiib_pcs1>;
33 pcs-handle-names = "sgmii", "qsgmii";
44 pcs-handle = <&pcsphy4>, <&qsgmiib_pcs2>;
45 pcs-handle-names = "sgmii", "qsgmii";
50 pcs-handle = <&pcsphy5>, <&qsgmiib_pcs3>;
51 pcs-handle-names = "sgmii", "qsgmii";
58 qsgmiib_pcs1: ethernet-pcs@1 {
59 compatible = "fsl,lynx-pcs";
63 qsgmiib_pcs2: ethernet-pcs@2 {
[all …]
H A Dtqmls1088a-mbls10xxa-mc.dtsi33 pcs-handle = <&pcs1>;
37 pcs-handle = <&pcs2>;
41 pcs-handle = <&pcs3_0>;
45 pcs-handle = <&pcs3_1>;
49 pcs-handle = <&pcs3_2>;
53 pcs-handle = <&pcs3_3>;
57 pcs-handle = <&pcs7_0>;
61 pcs-handle = <&pcs7_1>;
65 pcs-handle = <&pcs7_2>;
69 pcs-handle = <&pcs7_3>;
H A Dfsl-ls1088a-rdb.dts23 pcs-handle = <&pcs2>;
30 pcs-handle = <&pcs3_0>;
37 pcs-handle = <&pcs3_1>;
44 pcs-handle = <&pcs3_2>;
51 pcs-handle = <&pcs3_3>;
58 pcs-handle = <&pcs7_0>;
65 pcs-handle = <&pcs7_1>;
72 pcs-handle = <&pcs7_2>;
79 pcs-handle = <&pcs7_3>;
H A Dfsl-ls1088a-ten64.dts95 pcs-handle = <&pcs1>;
103 pcs-handle = <&pcs2>;
113 pcs-handle = <&pcs3_0>;
120 pcs-handle = <&pcs3_1>;
127 pcs-handle = <&pcs3_2>;
134 pcs-handle = <&pcs3_3>;
142 pcs-handle = <&pcs7_0>;
149 pcs-handle = <&pcs7_1>;
156 pcs-handle = <&pcs7_2>;
163 pcs-handle = <&pcs7_3>;
/linux/Documentation/networking/
H A Dsfp-phylink.rst219 should be used to configure the MAC when the MAC and PCS are not
249 10. Some Ethernet controllers work in pair with a PCS (Physical Coding Sublayer)
252 PCS whose operation is transparent, some other require dedicated PCS
254 provides a PCS abstraction through :c:type:`struct phylink_pcs <phylink_pcs>`.
256 Identify if your driver has one or more internal PCS blocks, and/or if
257 your controller can use an external PCS block that might be internally
260 If your controller doesn't have any internal PCS, you can go to step 11.
262 If your Ethernet controller contains one or several PCS blocks, create
263 one :c:type:`struct phylink_pcs <phylink_pcs>` instance per PCS block within
268 struct phylink_pcs pcs;
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/linux/drivers/net/phy/
H A Dphylink.c51 struct phylink_pcs *pcs; member
680 struct phylink_pcs *pcs = NULL; in phylink_validate_mac_and_pcs() local
684 /* Get the PCS for this interface mode */ in phylink_validate_mac_and_pcs()
686 pcs = pl->mac_ops->mac_select_pcs(pl->config, state->interface); in phylink_validate_mac_and_pcs()
687 if (IS_ERR(pcs)) in phylink_validate_mac_and_pcs()
688 return PTR_ERR(pcs); in phylink_validate_mac_and_pcs()
691 if (pcs) { in phylink_validate_mac_and_pcs()
692 /* The PCS, if present, must be setup before phylink_create() in phylink_validate_mac_and_pcs()
696 if (!pcs->ops) { in phylink_validate_mac_and_pcs()
697 phylink_err(pl, "interface %s: uninitialised PCS\n", in phylink_validate_mac_and_pcs()
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H A Dqt2025.rs59 // 3.41 5/10/25GBASE-R PCS test pattern seed B) for something else. in probe()
61 dev.write(C45::new(Mmd::PCS, 0x0026), 0x0e00)?; in probe()
62 dev.write(C45::new(Mmd::PCS, 0x0027), 0x0893)?; in probe()
63 dev.write(C45::new(Mmd::PCS, 0x0028), 0xa528)?; in probe()
64 dev.write(C45::new(Mmd::PCS, 0x0029), 0x0003)?; in probe()
70 dev.write(C45::new(Mmd::PCS, 0xe854), 0x00c0)?; in probe()
81 let mut dst_mmd = Mmd::PCS; in probe()
94 dev.write(C45::new(Mmd::PCS, 0xe854), 0x0040)?; in probe()
/linux/drivers/net/pcs/
H A DMakefile2 # Makefile for Linux PCS drivers
4 pcs_xpcs-$(CONFIG_PCS_XPCS) := pcs-xpcs.o pcs-xpcs-plat.o \
5 pcs-xpcs-nxp.o pcs-xpcs-wx.o
8 obj-$(CONFIG_PCS_LYNX) += pcs-lynx.o
9 obj-$(CONFIG_PCS_MTK_LYNXI) += pcs-mtk-lynxi.o
10 obj-$(CONFIG_PCS_RZN1_MIIC) += pcs-rzn1-miic.o
H A Dpcs-xpcs.c11 #include <linux/pcs/pcs-xpcs.h>
17 #include "pcs-xpcs.h"
20 container_of((pl_pcs), struct dw_xpcs, pcs)
137 return &xpcs->pcs; in xpcs_to_phylink_pcs()
545 static int xpcs_validate(struct phylink_pcs *pcs, unsigned long *supported, in xpcs_validate() argument
553 xpcs = phylink_pcs_to_xpcs(pcs); in xpcs_validate()
570 static unsigned int xpcs_inband_caps(struct phylink_pcs *pcs, in xpcs_inband_caps() argument
573 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); in xpcs_inband_caps()
635 static void xpcs_pre_config(struct phylink_pcs *pcs, phy_interface_t interface) in xpcs_pre_config() argument
637 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); in xpcs_pre_config()
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H A DKconfig3 # PCS Layer Configuration
6 menu "PCS device drivers"
18 This module provides helpers to phylink for managing the Lynx PCS
25 This module provides helpers to phylink for managing the LynxI PCS
33 on RZ/N1 SoCs. This PCS converts MII to RMII/RGMII or can be set in
/linux/Documentation/devicetree/bindings/net/
H A Dnvidia,tegra234-mgbe.yaml49 - const: eee-pcs
50 - const: rx-pcs-input
51 - const: rx-pcs-m
52 - const: rx-pcs
53 - const: tx-pcs
61 - const: pcs
137 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
138 "rx-pcs", "tx-pcs";
141 reset-names = "mac", "pcs";
H A Dfsl,fman-mdio.yaml41 Fman has internal MDIO for internal PCS(Physical
59 set when reading internal PCS registers. MDIO reads to
60 internal PCS registers may result in having the
64 PCS registers through MDIO. As a workaround, all internal
71 - For "fsl,fman-memac-mdio" compatible internal mdio bus, the PHY is PCS PHY.
72 The PCS PHY address should correspond to the value of the appropriate
/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp.h35 #include "phy-qcom-qmp-pcs-v2.h"
37 #include "phy-qcom-qmp-pcs-v3.h"
39 #include "phy-qcom-qmp-pcs-v4.h"
41 #include "phy-qcom-qmp-pcs-v4_20.h"
43 #include "phy-qcom-qmp-pcs-v5.h"
45 #include "phy-qcom-qmp-pcs-v5_20.h"
47 #include "phy-qcom-qmp-pcs-v6.h"
49 #include "phy-qcom-qmp-pcs-v6-n4.h"
51 #include "phy-qcom-qmp-pcs-v6_20.h"
53 #include "phy-qcom-qmp-pcs-v7.h"
H A Dphy-qcom-qmp-ufs.c27 #include "phy-qcom-qmp-pcs-ufs-v2.h"
28 #include "phy-qcom-qmp-pcs-ufs-v3.h"
29 #include "phy-qcom-qmp-pcs-ufs-v4.h"
30 #include "phy-qcom-qmp-pcs-ufs-v5.h"
31 #include "phy-qcom-qmp-pcs-ufs-v6.h"
44 /* PCS registers */
954 u16 pcs; member
962 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
969 const struct qmp_phy_init_tbl *pcs; member
983 /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
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H A Dphy-qcom-qmp-usbc.c29 #include "phy-qcom-qmp-pcs-misc-v3.h"
35 /* PCS registers */
289 u16 pcs; member
302 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
326 void __iomem *pcs; member
401 .pcs = 0xc00,
461 void __iomem *pcs = qmp->pcs; in qmp_usbc_init() local
487 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN); in qmp_usbc_init()
538 /* Tx, Rx, and PCS configurations */ in qmp_usbc_power_on()
545 qmp_configure(qmp->dev, qmp->pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); in qmp_usbc_power_on()
[all …]
H A Dphy-qcom-qmp-pcie-msm8996.c43 /* PCS registers */
144 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
176 * @pcs: iomapped memory space for lane's pcs
188 void __iomem *pcs; member
413 void __iomem *pcs = qphy->pcs; in qmp_pcie_msm8996_power_on() local
433 /* Tx, Rx, and PCS configurations */ in qmp_pcie_msm8996_power_on()
436 qmp_configure(qmp->dev, pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); in qmp_pcie_msm8996_power_on()
442 qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, in qmp_pcie_msm8996_power_on()
448 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_pcie_msm8996_power_on()
451 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], in qmp_pcie_msm8996_power_on()
[all …]
H A Dphy-qcom-qmp-usb-legacy.c24 #include "phy-qcom-qmp-pcs-misc-v3.h"
25 #include "phy-qcom-qmp-pcs-usb-v4.h"
26 #include "phy-qcom-qmp-pcs-usb-v5.h"
72 /* PCS registers */
483 u16 pcs; member
493 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
518 /* Offset from PCS to PCS_USB region */
528 void __iomem *pcs; member
757 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ in qmp_usb_legacy_init_dp_com()
770 void __iomem *pcs = qmp->pcs; in qmp_usb_legacy_init() local
[all …]
/linux/Documentation/devicetree/bindings/net/pcs/
H A Dfsl,lynx-pcs.yaml4 $id: http://devicetree.org/schemas/net/pcs/fsl,lynx-pcs.yaml#
7 title: NXP Lynx PCS
13 NXP Lynx 10G and 28G SerDes have Ethernet PCS devices which can be used as
19 const: fsl,lynx-pcs
36 qsgmii_pcs1: ethernet-pcs@1 {
37 compatible = "fsl,lynx-pcs";
H A Dmediatek,sgmiisys.yaml4 $id: http://devicetree.org/schemas/net/pcs/mediatek,sgmiisys.yaml#
13 The MediaTek SGMIISYS controller provides a SGMII PCS and some clocks
45 pcs:
47 description: MediaTek LynxI HSGMII PCS
84 - pcs
88 pcs: false
H A Dsnps,dw-xpcs.yaml4 $id: http://devicetree.org/schemas/net/pcs/snps,dw-xpcs.yaml#
7 title: Synopsys DesignWare Ethernet PCS
16 controlled by means of the IEEE std. Clause 45 registers set. The PCS can be
21 The PCS CSRs can be accessible either over the Ethernet MDIO bus or directly
83 PCS/PMA layer can be clocked by an internal reference clock source
111 ethernet-pcs@1f05d000 {
128 ethernet-pcs@0 {
/linux/drivers/clocksource/
H A Dtimer-pistachio.c70 struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs); in pistachio_clocksource_read_cycles() local
80 raw_spin_lock_irqsave(&pcs->lock, flags); in pistachio_clocksource_read_cycles()
81 overflow = gpt_readl(pcs->base, TIMER_CURRENT_OVERFLOW_VALUE, 0); in pistachio_clocksource_read_cycles()
82 counter = gpt_readl(pcs->base, TIMER_CURRENT_VALUE, 0); in pistachio_clocksource_read_cycles()
83 raw_spin_unlock_irqrestore(&pcs->lock, flags); in pistachio_clocksource_read_cycles()
96 struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs); in pistachio_clksrc_set_mode() local
99 val = gpt_readl(pcs->base, TIMER_CFG, timeridx); in pistachio_clksrc_set_mode()
105 gpt_writel(pcs->base, val, TIMER_CFG, timeridx); in pistachio_clksrc_set_mode()
110 struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs); in pistachio_clksrc_enable() local
114 gpt_writel(pcs->base, RELOAD_VALUE, TIMER_RELOAD_VALUE, timeridx); in pistachio_clksrc_enable()
/linux/tools/testing/selftests/bpf/
H A Djit_disasm_helpers.c30 __u32 pcs[MAX_LOCAL_LABELS]; member
47 * - if print_phase is true and ref_value is in labels->pcs, in lookup_symbol()
50 * in labels->pcs; in lookup_symbol()
54 if (labels->pcs[i] == ref_value) in lookup_symbol()
58 labels->pcs[labels->cnt++] = ref_value; in lookup_symbol()
124 qsort(labels.pcs, labels.cnt, sizeof(*labels.pcs), cmp_u32); in disasm_one_func()
144 label_pc = bsearch(&pc, labels.pcs, labels.cnt, sizeof(*labels.pcs), cmp_u32); in disasm_one_func()
148 label = labels.names[label_pc - labels.pcs]; in disasm_one_func()
/linux/drivers/leds/simple/
H A DKconfig8 This option enables support for the LEDs of several Industrial PCs
21 This option enables support for the LEDs of several Industrial PCs
34 This option enables support for the LEDs of several Industrial PCs
47 This option enables support for the LEDs of several Industrial PCs

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