pcie\-root\-port\-2 (full) in projects: illumos-gate

Project(s)

Full Search
Definition
Symbol
File Path
History
Type

Searched +full:pcie +full:- +full:root +full:- +full:port +full:- +full:2 (Results 1 – 25 of 54) sorted by relevance

12 3

/illumos-gate/usr/src/data/hwdata/
H A D	pci.ids	`5 # Date: 2025-06-09 03:15:02 8 # the PCI ID Project at https://pci-ids.ucw.cz/. 14 # (version 2 or higher) or the 3-clause BSD License. 25 # device device_name <-- single tab 26 # subvendor subdevice subsystem_name <-- two tabs 30 # This is a relabelled RTL-8139 31 8139 AT-2500TX V3 Ethernet 41 7a09 PCI-to-PCI Bridge 51 7a19 PCI-to-PCI Bridge 57 7a29 PCI-to-PCI Bridge [all …]`
/illumos-gate/usr/src/uts/common/io/pciex/
H A D	pcie.c	29 * PCIe Initialization 30 * ------------------- 32 * The PCIe subsystem is split about and initializes itself in a couple of 33 * different places. This is due to the platform-specific nature of initializing 37 * large chunk of PCIe-specific initialization. 41 * at system power on. These devices may or may not be hot-pluggable. In 42 * particular, this happens in a platform-specific way right now. In general, we 50 * the system for PCIe are: 54 * o Non-prefetchable memory 61 * Currently it is up to platform-specific code (which should ideally be [all …]
H A D	pcie_fault.c	41 #include <sys/pcie.h> 68 (bit & (1 << (adv->pcie_adv_ctl & PCIE_AER_CTL_FST_ERR_PTR_MASK))) 71 (PCIE_HAS_AER(pfd_p->pe_bus_p) && \ 75 (bit & (1 << (adv->pcie_sue_ctl & PCIE_AER_SCTL_FST_ERR_PTR_MASK))) 78 (PCIE_HAS_AER(pfd_p->pe_bus_p) && \ 86 (PCIE_ADV_REG(pfd_p)->pcie_ce_status & PCIE_AER_CE_AD_NFE) 88 /* PCIe Fault Fabric Error analysis table / 151 / PCIe Fabric Handle Lookup Support Functions. / 177 pcie_bus_t rbus_p = PCIE_DIP2BUS(bus_p->bus_rp_dip); in pf_eh_exit() 180 uint_t intr_type = PCIE_ROOT_EH_SRC(root_pfd_p)->intr_type; in pf_eh_exit() [all …]
H A D	pcieb.c	31 * Common x86 and SPARC PCI-E to PCI bus bridge nexus driver 34 * ---------- 36 * The PCI Express (PCIe) specification defines that all of the PCIe devices in 40 * fabric. The entry point to that fabric is called a root complex and the 41 * fabric terminates at a what is called an endpoint, which is really just PCIe 45 * The PCIe specification states that every link on the system has a virtual 46 * PCI-to-PCI bridge. This allows PCIe devices to still be configured the same 50 * connect traditional PCI and PCI-X devices into them. 52 * The PCIe specification refers to upstream and downstream ports. Upstream 53 * ports are considered closer the root complex and downstream ports are closer [all …]
/illumos-gate/usr/src/uts/common/sys/
H A D	pcie_impl.h	`34 #include <sys/pcie.h> 39 PCIE_DIP2BUS(dip)->bus_bdf 41 PCIE_DIP2BUS(dip)->bus_bdg_secbus 43 PCIE_DIP2BUS(dip)->bus_pcie2pci_secbus 59 #define PCIE_DIP2PFD(dip) (PCIE_DIP2BUS(dip))->bus_pfd 60 #define PCIE_PFD2BUS(pfd_p) pfd_p->pe_bus_p 61 #define PCIE_PFD2DIP(pfd_p) PCIE_PFD2BUS(pfd_p)->bus_dip 62 #define PCIE_BUS2DIP(bus_p) bus_p->bus_dip 64 #define PCIE_BUS2DOM(bus_p) bus_p->bus_dom 70 #define PCIE_IS_PCIE(bus_p) (bus_p->bus_pcie_off) [all …]`
H A D	pcie.h	46 #define PCIE_PCIECAP 0x02 /* PCI-e Capability Reg / 56 #define PCIE_ROOTCTL 0x1C / Root Control / 57 #define PCIE_ROOTCAP 0x1E / Root Capabilities / 58 #define PCIE_ROOTSTS 0x20 / Root Status / 59 #define PCIE_DEVCAP2 0x24 / Device Capability 2 / 60 #define PCIE_DEVCTL2 0x28 / Device Control 2 / 61 #define PCIE_DEVSTS2 0x2A / Device Status 2 / 62 #define PCIE_LINKCAP2 0x2C / Link Capability 2 / 63 #define PCIE_LINKCTL2 0x30 / Link Control 2 / 64 #define PCIE_LINKSTS2 0x32 / Link Status 2 */ [all …]
/illumos-gate/usr/src/uts/intel/io/pciex/
H A D	pcieb_x86.c	35 #include <sys/pcie.h> 60 hdlp->ahi_err_mutexp = &pcieb->pcieb_err_mutex; in pcieb_set_prot_scan() 61 hdlp->ahi_peekpoke_mutexp = &pcieb->pcieb_peek_poke_mutex; in pcieb_set_prot_scan() 62 hdlp->ahi_scan_dip = dip; in pcieb_set_prot_scan() 63 hdlp->ahi_scan = pcieb_peekpoke_cb; in pcieb_set_prot_scan() 77 ddi_ctlops, &pcieb->pcieb_err_mutex, in pcieb_plat_peekpoke() 78 &pcieb->pcieb_peek_poke_mutex, in pcieb_plat_peekpoke() 99 pcieb_intel_serr_workaround(dip, pcieb->pcieb_no_aer_msi); in pcieb_intel_error_workaround() 157 vendor_id = bus_p->bus_dev_ven_id & 0xFFFF; in pcieb_plat_msi_supported() 158 device_id = bus_p->bus_dev_ven_id >> 16; in pcieb_plat_msi_supported() [all …]
H A D	pcie_nvidia.c	28 * Library file that has code for PCIe booting 34 #include <sys/pcie.h> 40 * PCI Configuration (Nvidia chipsets, PCIe) related library functions 67 while (cap_count-- && capsp >= PCI_CAP_PTR_OFF) { in check_if_device_is_pciex() 74 cmn_err(CE_CONT, "PCI-Express (%x,%x,%x) " in check_if_device_is_pciex() 78 status = (pci_getw_func)(bus, dev, func, capsp + 2); in check_if_device_is_pciex() 80 See section 7.8.2 of PCI-Express Base Spec v1.0a in check_if_device_is_pciex() 81 * for Device/Port Type. in check_if_device_is_pciex() 115 * PCI-Express device in the system. 148 * the pci-drivers alias, their only requirement for in look_for_any_pciex_device() [all …]
/illumos-gate/usr/src/uts/sun4v/io/px/
H A D	px_err.c	87 px_rc_err_t epkt = (px_rc_err_t )fault_p->px_intr_payload; in px_err_cb_intr() 104 px_rc_err_t epkt = (px_rc_err_t )fault_p->px_intr_payload; in px_err_dmc_pec_intr() 149 /* Add an PCIE PF_DATA Entry */ in px_err_fill_pfd() 150 switch (epkt->rc_descr.block) { in px_err_fill_pfd() 156 if (epkt->rc_descr.H) { in px_err_fill_pfd() 157 fault_bdf = (pcie_req_id_t)(epkt->hdr[0] >> 16); in px_err_fill_pfd() 158 PFD_AFFECTED_DEV(pfd_p)->pe_affected_flags = in px_err_fill_pfd() 160 PFD_AFFECTED_DEV(pfd_p)->pe_affected_bdf = in px_err_fill_pfd() 166 dir = pec_p->pec_descr.dir; in px_err_fill_pfd() 170 pec_p->pec_descr.U) { in px_err_fill_pfd() [all …]
/illumos-gate/usr/src/uts/sun4/io/px/
H A D	px_fm.c	71 dev_info_t dip = px_p->px_dip; in px_fm_attach() 74 px_p->px_fm_cap = DDI_FM_EREPORT_CAPABLE \| DDI_FM_ERRCB_CAPABLE \| in px_fm_attach() 80 ddi_fm_init(dip, &px_p->px_fm_cap, &px_p->px_fm_ibc); in px_fm_attach() 85 ASSERT(px_p->px_fm_cap && in px_fm_attach() 91 mutex_init(&px_p->px_fm_mutex, NULL, MUTEX_DRIVER, in px_fm_attach() 92 (void )px_p->px_fm_ibc); in px_fm_attach() 94 px_p->px_pfd_idx = 0; in px_fm_attach() 96 pcie_rc_init_pfd(dip, &px_p->px_pfd_arr[i]); in px_fm_attach() 97 PCIE_DIP2PFD(dip) = px_p->px_pfd_arr; in px_fm_attach() 100 bus_p->bus_rp_bdf = px_p->px_bdf; in px_fm_attach() [all …]
H A D	px_space.c	`45 * 1234181 - obp should set latency timer registers in pci 59 uint_t px_mmu_error_intr_enable = (uint_t)-1; 62 uint_t px_error_intr_enable = (uint_t)-1; 76 uint64_t px_perr_fatal = -1ull; 77 uint64_t px_serr_fatal = -1ull; 81 char px_panic_rc_msg[] = " PCIe root complex"; 82 char px_panic_rp_msg[] = " PCIe root port"; 83 char px_panic_fab_msg[] = " PCIe fabric"; 89 * with multi-function devices or bus bridges. 94 * Setting the flag to non-zero causes the ino handler routine to [all …]`
H A D	px_ioapi.h	38 * cpuid - A unique opaque value which represents a target cpu. 40 * devhandle - Device handle. The device handle uniquely 42 * the lower 28-bits of the hi-cell of the first 46 * devino - Device Interrupt Number. An unsigned integer representing 49 * sysino - System Interrupt Number. A 64-bit unsigned integer 52 * intr_state - A flag representing the interrupt state for a 57 * INTR_DELIVERED 2 59 * intr_valid_state - A flag representing the 'valid' state for 75 INTR_DELIVERED_STATE = (uint32_t)2 86 * tsbnum - TSB Number. Identifies which io-tsb is used. [all …]
H A D	px_fm.h	`41 #define PX_LIB_CALL 2 44 * Definition of Fire internal error severity - 52 * No-panic Errors that don't directly result in panic'ing the system. 53 * No-Error When an interrupt occured and no errors were seen 61 #define PX_PROTECTED (0x1 << 2) 65 #define PX_HB (0x1 << 2) 70 * Generic PCIe Root Port Error Handling 90 uint32_t rsvd4; /* root err status */`
/illumos-gate/usr/src/cmd/pcieadm/
H A D	pcieadm_cfgspace.c	18 * space and many of the capabilities. There are multiple sub-commands that 19 * vector into the same logic (e.g. 'save-cfgspace' and 'show-cfgspace'). In 24 * human name. The short name is a dot-delineated name. When in parsable 28 * 'pcie.linkcap.maxspeed', in parsable mode you'll only get that; however, 29 * in non-parsable mode, you'll get an indication of the capability and 43 * o Currently designated vendor-specific capabilities aren't included here (or 44 * any specific vendor-specific capabilities for that matter). If they are 46 * sub-capability as we did with HyperTransport. 53 #include <sys/pcie.h> 114 * Enough space for up to an 8-bit fields worth of values [all …]
/illumos-gate/usr/src/cmd/fm/modules/common/fabric-xlate/
H A D	fx_fabric.c	31 #include <sys/pcie.h> 33 #include "fabric-xlate.h" 59 /* Translate Fabric ereports to ereport.io.pci.sec-* / 142 / Translate Fabric ereports to ereport.io.pcix.sec-* / 174 If the RP is not a PCIe compliant RP or does not support AER, rely on the 188 data->nvl = nvl; in fab_pci_fabric_to_data() 191 FAB_LOOKUP(16, "bdf", &data->bdf); in fab_pci_fabric_to_data() 192 FAB_LOOKUP(16, "device_id", &data->device_id); in fab_pci_fabric_to_data() 193 FAB_LOOKUP(16, "vendor_id", &data->vendor_id); in fab_pci_fabric_to_data() 194 FAB_LOOKUP(8, "rev_id", &data->rev_id); in fab_pci_fabric_to_data() [all …]
H A D	fx_epkt.c	`28 #include "fabric-xlate.h" 36 uint32_t pcie_ue_sts; /* Equivalent PCIe UE Status */ 53 EPKT_DESC(PORT, PIO, IRR, RCA, WRITE), 56 EPKT_DESC(PORT, PIO, IRR, RUR, WRITE), 59 EPKT_DESC(PORT, PIO, IRR, INV, RDWR), 62 EPKT_DESC(PORT, PIO, IRR, TO, READ), 64 EPKT_DESC(PORT, PIO, IRR, TO, WRITE), 67 EPKT_DESC(PORT, PIO, IRR, UC, IRR), 70 EPKT_DESC(PORT, LINK, FC, TO, IRR), 80 data->nvl = nvl; in fab_epkt_to_data() [all …]`
H A D	fx_subr.c	35 #include "fabric-xlate.h" 72 * Create the correct ROOT FMRI from PCIe leaf fabric ereports. Used in fab_prep_basic_erpt() 77 /* Create the correct PCIe RC new_detector aka FMRI / in fab_prep_basic_erpt() 95 nvlist_t nvl = data->nvl; in fab_send_tgt_erpt() 103 tgt_trans = data->pcie_ue_tgt_trans; in fab_send_tgt_erpt() 104 tgt_addr = data->pcie_ue_tgt_addr; in fab_send_tgt_erpt() 105 tgt_bdf = data->pcie_ue_tgt_bdf; in fab_send_tgt_erpt() 107 tgt_trans = data->pcie_sue_tgt_trans; in fab_send_tgt_erpt() 108 tgt_addr = data->pcie_sue_tgt_addr; in fab_send_tgt_erpt() 109 tgt_bdf = data->pcie_sue_tgt_bdf; in fab_send_tgt_erpt() [all …]
/illumos-gate/usr/src/uts/common/sys/plat/
H A D	pci_prd.h	22 * This file forms the platform-specific interfaces that a given platform must 25 * o Any root complexes that do not show up through the use of normal scanning 26 * o Available resources per root-port including: 31 * o The naming of slots (the platform uses the PCIe default) 88 * that platforms will just return 0xff (PCI_MAX_BUS_NUM - 1) unless for some 96 * root complexes. 101 * Originally when only using BIOS-derived (pre-ACPI) sources on i86pc, the 103 * this exists as a way to indicate that resources on each root complex are 110 * PCI root complexes that it might know about which might not be discovered 151 PCI_PRD_COMPAT_SUBSYS = 1 << 2
/illumos-gate/usr/src/lib/fm/topo/modules/common/pcibus/
H A D	pcibus.c	38 #include <sys/pcie.h> 102 return (-1); in _topo_init() 159 return (-1); in hostbridge_asdevice() 162 return (-1); in hostbridge_asdevice() 181 * In general, almost all UFMs are device-wide. That is, in a in pciexfn_add_ufm() 182 * multi-function device, there is still a single global firmware image. in pciexfn_add_ufm() 186 * add support for hardware that has per-function UFMs, then we should in pciexfn_add_ufm() 224 /* If this is the first child under root, get root's ptn / in pciexfn_declare() 241 Populate the excap with correct PCIe device type. in pciexfn_declare() 244 * excap device-type device-type excap Class Code in pciexfn_declare() [all …]
/illumos-gate/usr/src/uts/common/io/qede/579xx/hsi/hw/
H A D	reg_addr_e5.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 65 … 0x002000UL //Access:RW DataWidth:0x20 // Control and status interface for PCIE IP. 84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 85 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 86 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 87 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 89 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 91 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
H A D	reg_addr_k2.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 65 … 0x002000UL //Access:RW DataWidth:0x20 // Control and status interface for PCIE IP. 84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 85 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 86 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 87 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 89 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 91 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
H A D	reg_addr.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 65 … 0x002000UL //Access:RW DataWidth:0x20 // Control and status interface for PCIE IP. 85 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 86 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 87 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 88 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 90 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 92 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
H A D	reg_addr_ah_compile15.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 65 …0x002000UL //Access:RW DataWidth:0x20 Control and status interface for PCIE IP. Chips: BB_A0 B… 85 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 87 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 91 …tifies the PCI adapter. This value can be written by firmware through the PCIE private register sp… 93 …his register identifies the device on the PCIE adapter. This value can be written by firmware thro… 96 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 98 … has_mem_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
H A D	reg_addr_bb.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 65 … 0x002000UL //Access:RW DataWidth:0x20 // Control and status interface for PCIE IP. 84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 85 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 86 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 87 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 89 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 91 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
/illumos-gate/usr/src/lib/fm/topo/modules/i86pc/x86pi/
H A D	x86pi.c	100 return (-1); in _topo_init() 107 return (-1); in _topo_init() 115 return (-1); in _topo_init() 159 return (-1); in x86pi_enum() 164 ((gethrtime() - starttime)/MICROSEC)); in x86pi_enum() 197 return (topo_mod_enummap(mod, x86pi->t_parent, in x86pi_enum_start() 198 "i86pc-legacy", FM_FMRI_SCHEME_HC)); in x86pi_enum_start() 201 x86pi->priv = (void *)shp; in x86pi_enum_start() 206 return (-1); in x86pi_enum_start() 213 rv = x86pi_enum_gentopo(mod, x86pi->t_parent); in x86pi_enum_start() [all …]

12 3