| /freebsd/sys/contrib/device-tree/Bindings/pci/ |
| H A D | nvidia,tegra194-pcie.txt | 4 and thus inherits all the common properties defined in snps,dw-pcie.yaml and
5 snps,dw-pcie-ep.yaml.
10 - power-domains: A phandle to the node that controls power to the respective
20 "include/dt-bindings/power/tegra194-powergate.h" file.
21 - reg: A list of physical base address and length pairs for each set of
22 controller registers. Must contain an entry for each entry in the reg-names
24 - reg-names: Must include the following entries:
26 "config": As per the definition in snps,dw-pcie.yaml
32 - interrupts: A list of interrupt outputs of the controller. Must contain an
33 entry for each entry in the interrupt-names property.
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| H A D | pci-ep-bus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/pci-ep-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common Properties for PCI MFD EP with Peripherals Addressable from BARs
10 - A. della Porta <andrea.porta@suse.com>
13 Define a generic node representing a PCI endpoint which contains several sub-
19 '#address-cells':
22 '#size-cells':
32 - maximum: 5 # The BAR number
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| H A D | designware-pcie.txt | 4 - compatible:
5 "snps,dw-pcie" for RC mode;
6 "snps,dw-pcie-ep" for EP mode;
7 - reg: For designware cores version < 4.80 contains the configuration
10 - reg-names: Must be "config" for the PCIe configuration space and "atu" for
15 - #address-cells: set to <3>
16 - #size-cells: set to <2>
17 - device_type: set to "pci"
18 - ranges: ranges for the PCI memory and I/O regions
19 - #interrupt-cells: set to <1>
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| H A D | rockchip-dw-pcie-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Niklas Cassel <cassel@kernel.org>
15 snps,dw-pcie-ep.yaml.
18 - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
19 - $ref: /schemas/pci/rockchip-dw-pcie-common.yaml#
24 - rockchip,rk3568-pcie-ep
25 - rockchip,rk3588-pcie-ep
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| H A D | snps,dw-pcie-ep.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Endpoint controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie-ep
23 - compatible
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| H A D | ti,j721e-pci-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: TI J721E PCI EP (PCIe Wrapper)
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - const: ti,j721e-pcie-ep
17 - const: ti,j784s4-pcie-ep
18 - description: PCIe EP controller in AM64
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| H A D | ti-pci.txt | 1 TI PCI Controllers
4 - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
5 Should be "ti,dra7-pcie-ep" for EP (deprecated)
6 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
7 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
8 Should be "ti,dra726-pcie-rc" for dra72x in RC mode
9 Should be "ti,dra726-pcie-ep" for dra72x in EP mode
10 - phys : list of PHY specifiers (used by generic PHY framework)
11 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
13 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
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| H A D | fsl,imx6q-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lucas Stach <l.stach@pengutronix.de>
11 - Richard Zhu <hongxing.zhu@nxp.com>
15 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
19 See fsl,imx6q-pcie-ep.yaml for details on the Endpoint mode device tree
25 - fsl,imx6q-pcie
26 - fsl,imx6sx-pcie
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| H A D | fsl,imx6q-pcie-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lucas Stach <l.stach@pengutronix.de>
11 - Richard Zhu <hongxing.zhu@nxp.com>
15 thus inherits all the common properties defined in snps,dw-pcie-ep.yaml.
22 - fsl,imx8mm-pcie-ep
23 - fsl,imx8mq-pcie-ep
24 - fsl,imx8mp-pcie-ep
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| H A D | rockchip,rk3399-pcie-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Lin <shawn.lin@rock-chips.com>
13 - $ref: /schemas/pci/pci-ep.yaml#
14 - $ref: rockchip,rk3399-pcie-common.yaml#
18 const: rockchip,rk3399-pcie-ep
22 reg-names:
24 - const: apb-base
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| H A D | axis,artpec6-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pci/axis,artpec6-pcie.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Axis ARTPEC-6 PCIe host controller
11 - Jesper Nilsson <jesper.nilsson@axis.com>
21 - axis,artpec6-pcie
22 - axis,artpec6-pcie-ep
23 - axis,artpec7-pcie
24 - axis,artpec7-pcie-ep
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| H A D | qcom,pcie-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
15 - enum:
16 - qcom,sa8775p-pcie-ep
17 - qcom,sar2130p-pcie-ep
18 - qcom,sdx55-pcie-ep
19 - qcom,sm8450-pcie-ep
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| H A D | cdns,cdns-pcie-ep.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence PCIe EP Controller
10 - Tom Joseph <tjoseph@cadence.com>
13 - $ref: cdns-pcie-ep.yaml#
17 const: cdns,cdns-pcie-ep
22 reg-names:
24 - const: reg
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| H A D | nvidia,tegra194-pcie-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
16 inherits all the common properties defined in snps,dw-pcie-ep.yaml. Some
23 Note: On Tegra194's P2972-0000 platform, only C5 controller can be enabled to
29 - nvidia,tegra194-pcie-ep
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| H A D | rockchip,rk3399-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Lin <shawn.lin@rock-chips.com>
13 - $ref: /schemas/pci/pci-host-bridge.yaml#
14 - $ref: rockchip,rk3399-pcie-common.yaml#
18 const: rockchip,rk3399-pcie
22 reg-names:
24 - const: axi-base
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| H A D | layerscape-pci.txt | 4 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
7 which is used to describe the PLL settings at the time of chip-reset.
15 - compatible: should contain the platform identifier such as:
17 "fsl,ls1021a-pcie"
18 "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"
19 "fsl,ls2088a-pcie"
20 "fsl,ls1088a-pcie"
21 "fsl,ls1046a-pcie"
22 "fsl,ls1043a-pcie"
23 "fsl,ls1012a-pcie"
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| H A D | axis,artpec6-pcie.txt | 1 * Axis ARTPEC-6 PCIe interface
4 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
7 - compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode;
8 "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode;
9 "axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode;
10 "axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode;
11 - reg: base addresses and lengths of the PCIe controller (DBI),
13 - reg-names: Must include the following entries:
14 - "dbi"
15 - "phy"
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| /freebsd/sys/contrib/openzfs/lib/libzutil/os/linux/ |
| H A D | zutil_device_path_os.c | 1 // SPDX-License-Identifier: CDDL-1.0
10 * or https://opensource.org/licenses/CDDL-1.0.
55 return (-1); in zfs_append_partition()
57 (void) strcat(path, "-part1"); in zfs_append_partition()
61 return (-1); in zfs_append_partition()
63 if (isdigit(path[len-1])) { in zfs_append_partition()
77 * forms: "-partX", "pX", or "X", where X is a string of digits. The second
80 * expression "^([hsv]|xv)d[a-z]+", i.e. a scsi, ide, virtio or xen disk.
92 if ((part = strstr(tmp, "-part")) && part != tmp) { in zfs_strip_partition()
95 part > tmp + 1 && isdigit(*(part-1))) { in zfs_strip_partition()
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| /freebsd/sys/contrib/device-tree/Bindings/misc/ |
| H A D | pci1de4,1.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RaspberryPi RP1 MFD PCI device
10 - A. della Porta <andrea.porta@suse.com>
13 The RaspberryPi RP1 is a PCI multi function device containing
16 The peripherals are accessed by addressing the PCI BAR1 region.
19 - $ref: /schemas/pci/pci-ep-bus.yaml
26 - const: pci1de4,1
28 '#interrupt-cells':
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| /freebsd/sys/dev/ufshci/ |
| H A D | ufshci_pci.c | 1 /*-
5 * SPDX-License-Identifier: BSD-2-Clause
11 #include <sys/bus.h>
18 #include <dev/pci/pcireg.h>
19 #include <dev/pci/pcivar.h>
44 DRIVER_MODULE(ufshci, pci, ufshci_pci_driver, 0, 0);
67 struct _pcsid *ep = pci_ids; in ufshci_pci_probe() local
69 while (ep->devid && ep->devid != devid) in ufshci_pci_probe()
70 ++ep; in ufshci_pci_probe()
72 if (ep->devid) { in ufshci_pci_probe()
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| /freebsd/sys/contrib/alpine-hal/ |
| H A D | al_hal_pcie.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
38 * @defgroup grouppcie PCI Express Controller
43 * - Port initialization
44 * - Link operation
45 * - Interrupts transactions generation (Endpoint mode).
46 * - Configuration Access management functions
47 * - Internal Translation Unit programming
50 * - PCIe transactions generation and reception (except interrupts as mentioned
53 * - Configuration Access: those transactions are generated automatically by
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| /freebsd/share/man/man4/ |
| H A D | ral.4 | 1 .\"-
2 .\" SPDX-License-Identifier: ISC
4 .\" Copyright (c) 2005-2010 Damien Bergamini <damien.bergamini@free.fr>
28 .Bd -ragged -offset indent
39 .Bd -literal -offset indent
45 driver supports PCI/PCIe/CardBus wireless adapters based on the Ralink RT2500,
62 This chipset uses the MIMO (multiple-input multiple-output) technology with
67 The RT2700 chipset is a low-cost version of the RT2800 chipset.
80 The RT3090 chipset is the first generation of single-chip 802.11n adapters
108 The RT3900E chipset is a single-chip 802.11n adapters from Ralink.
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| /freebsd/sys/dev/nvme/ |
| H A D | nvme_pci.c | 1 /*-
2 * Copyright (C) 2012-2016 Intel Corporation
30 #include <sys/bus.h>
36 #include <dev/pci/pcireg.h>
37 #include <dev/pci/pcivar.h>
66 DRIVER_MODULE(nvme, pci, nvme_pci_driver, NULL, NULL);
81 { 0x09538086, 1, 0x3704, "DC P3500 SSD [Add-in Card]" },
83 { 0x09538086, 1, 0x3709, "DC P3600 SSD [Add-in Card]" },
100 nvme_match(uint32_t devid, uint16_t subdevice, struct _pcsid *ep) in nvme_match() argument
102 if (devid != ep->devid) in nvme_match()
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| /freebsd/usr.sbin/pciconf/ |
| H A D | pciconf.c | 38 #include <dev/pci/pcireg.h>
93 "usage: pciconf -l [-BbcevV] [device]\n" in usage()
94 " pciconf -a device\n" in usage()
95 " pciconf -r [-b | -h] device addr[:addr2]\n" in usage()
96 " pciconf -w [-b | -h] device addr value\n" in usage()
97 " pciconf -D [-b | -h | -x] device bar [start [count]]" in usage()
113 while ((c = getopt(argc, argv, "aBbcDehlrwVvx")) != -1) { in main()
236 if (ioctl(fd, PCIOCGETCONF, &pc) == -1) in list_devs()
248 warnx("PCI device list changed, please try again"); in list_devs()
263 printf("%s%d@pci%d:%d:%d:%d:" in list_devs()
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| /freebsd/tools/tools/pciroms/ |
| H A D | pciroms.c | 44 #define _PATH_DEVPCI "/dev/pci"
65 * This is set to a safe physical base address in PCI range for my Vaio.
69 * This is the hole between the APIC and the BIOS (FED00000-FEDFFFFF);
95 char *ep; in main() local
97 err = -1; in main()
98 pci_fd = -1; in main()
101 ep = NULL; in main()
104 while ((ch = getopt(argc, argv, "sb:h")) != -1) in main()
116 argc -= optind; in main()
122 base_addr_max = strtoumax(base_addr_string, &ep, 16); in main()
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