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/linux/drivers/net/wireless/intel/iwlwifi/pcie/
H A Dctxt-info.c68 if (!dram->paging) { in iwl_pcie_ctxt_info_free_paging()
73 /* free paging*/ in iwl_pcie_ctxt_info_free_paging()
75 dma_free_coherent(trans->dev, dram->paging[i].size, in iwl_pcie_ctxt_info_free_paging()
76 dram->paging[i].block, in iwl_pcie_ctxt_info_free_paging()
77 dram->paging[i].physical); in iwl_pcie_ctxt_info_free_paging()
79 kfree(dram->paging); in iwl_pcie_ctxt_info_free_paging()
81 dram->paging = NULL; in iwl_pcie_ctxt_info_free_paging()
91 if (WARN(dram->paging, in iwl_pcie_init_fw_sec()
92 "paging shouldn't already be initialized (%d pages)\n", in iwl_pcie_init_fw_sec()
105 dram->paging = kzalloc_objs(*dram->paging, paging_cnt); in iwl_pcie_init_fw_sec()
[all …]
/linux/arch/arc/include/asm/
H A Dpgtable-levels.h7 * Helpers for implemenintg paging levels
16 * 2 level paging setup for software walked MMUv3 (ARC700) and MMUv4 (HS)
55 * A default 3 level paging testing setup in software walked MMU
57 * A default 4 level paging testing setup in software walked MMU
99 * 1st level paging: pgd
106 /* In 4 level paging, p4d_* macros work on pgd */
116 * 2nd level paging: pud
126 * In 3 level paging, pud_* macros work on pgd
127 * In 4 level paging, pud_* macros work on pud
138 * 3rd level paging: pmd
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/linux/arch/x86/include/asm/
H A Dcrash_reserve.h15 * the upper limit of system RAM in 4-level paging mode. Since the kdump
16 * jump could be from 5-level paging to 4-level paging, the jump will fail if
18 * no good way to detect the paging mode of the target kernel which will be
H A Dboot.h40 * mapping of the 4G of RAM in 4-level paging mode:
45 * The additional level5 table needed for 5-level paging is allocated from
55 * - 5-level paging needs 1 level5 table;
H A Dprocessor-flags.h29 * that the top-level paging structure is encrypted.
34 * paging structure.
H A Dx86_init.h70 * struct x86_init_paging - platform specific paging functions
71 * @pagetable_init: platform specific paging initialization call to setup
179 struct x86_init_paging paging; member
/linux/arch/x86/realmode/rm/
H A Dtrampoline_64.S180 # Enable paging and in turn activate Long Mode.
196 * paging and complete the switch to legacy 32-bit mode.
218 * 32-bit mode (to handle 4-level vs. 5-level paging), and to (re)load
225 /* Check if paging mode has to be changed */
231 /* Paging mode is correct proceed in 64-bit mode */
251 * To switch between 4- and 5-level paging modes, it is necessary
252 * to disable paging. This must be done in the compatibility mode.
H A Dreboot.S31 /* Disable paging to drop us out of long mode */
70 * This is 16-bit protected mode code to disable paging and the cache,
79 * Clears all the flags except ET, especially PG (paging), PE
81 * save). Flushes the TLB after paging has been disabled. Sets CD and
/linux/Documentation/virt/kvm/x86/
H A Dmmu.rst52 pte page table entry (used also to refer generically to paging structure
56 tdp two dimensional paging (vendor neutral term for NPT and EPT)
63 of the current paging mode and cr3 during guest entry, as well as
64 two-dimensional paging (AMD's NPT and Intel's EPT). The emulated hardware
76 - when guest paging is disabled, we translate guest physical addresses to
78 - when guest paging is enabled, we translate guest virtual addresses, to
129 one paging structure entry. These are always the lowest level of the
139 paging: gva->gpa->hpa
140 paging, tdp: (gva->)gpa->hpa
152 The level in the shadow paging hierarchy that this shadow page belongs to.
[all …]
/linux/arch/x86/boot/compressed/
H A Dmem_encrypt.S239 * The check makes use of the fact that all memory is encrypted when paging is
246 * when paging is off the random data will be stored encrypted in main memory.
248 * Then paging is enabled. When the C-bit position is correct all memory is
280 /* Enable paging to see if encryption is active */
282 movl $(X86_CR0_PG | X86_CR0_PE), %ecx /* Enable Paging and Protected mode */
/linux/drivers/net/wireless/intel/iwlwifi/fw/api/
H A Dpaging.h13 * struct iwl_fw_paging_cmd - paging layout
15 * Send to FW the paging layout in the driver.
/linux/arch/x86/mm/
H A Dmmap.c176 * With 4-level paging this request succeeds, but the resulting mapping
182 * With 5-level paging this request would be granted and result in a
192 * fails on a 4-level paging machine but succeeds on a 5-level paging
/linux/tools/testing/selftests/kvm/
H A Ddemand_paging_test.c3 * KVM demand paging test
198 * Set up user fault fd to handle demand paging in run_test()
230 pr_info("Per-vcpu demand paging rate:\t%f pgs/sec/vcpu\n", in run_test()
232 pr_info("Overall demand paging rate:\t%f pgs/sec\n", in run_test()
256 " FD handler to simulate demand paging\n" in help()
/linux/arch/x86/platform/efi/
H A Defi_stub_32.S35 /* disable paging */
52 /* re-enable paging */
/linux/drivers/infiniband/
H A DKconfig48 bool "InfiniBand on-demand paging support"
55 On demand paging support for the InfiniBand subsystem.
/linux/tools/testing/selftests/mm/
H A Dva_high_addr_switch.sh6 # This is a test for mmap behavior with 5-level paging. This script wraps the
53 skip "$0: System does not use Radix MMU, required for 5-level paging"
/linux/arch/x86/hyperv/
H A Dhv_trampoline.S25 * o CR0 is set to 0x0021: PE(prot mode) and NE are set, paging is disabled
62 /* Turn paging on using the temp 32bit trampoline page table */
/linux/tools/testing/selftests/kvm/x86/
H A Dvmx_nested_la57_state_test.c6 * is using 5-level paging and the L2 guest is using 4-level paging.
/linux/arch/x86/kvm/mmu/
H A Dpaging_tmpl.h27 #define FNAME(name) paging##64_##name
40 #define FNAME(name) paging##32_##name
274 * For EPT and PAE paging (both variants), bit 7 is either reserved at in FNAME()
280 * 32-bit paging requires special handling because bit 7 is ignored if in FNAME()
343 * FIXME: on Intel processors, loads of the PDPTE registers for PAE paging in FNAME()
345 * processor to set the dirty flag in any EPT paging-structure entry. in FNAME()
610 * Fetch a shadow pte for a specific level in the paging hierarchy.
932 * all other paging modes will create a read-only SPTE if in FNAME()
/linux/Documentation/admin-guide/hw-vuln/
H A Dmultihit.rst52 paging structure so that the same linear address using large page size (2 MB, 4
117 EPT paging mechanism used by nested virtualization is vulnerable, because
120 non-executable in all shadow paging modes.
/linux/drivers/iommu/amd/
H A Dnested.c42 /* Valid Guest Paging Mode values are 0 and 1 */ in validate_gdte_nested()
53 * the Guest Paging Mode in validate_gdte_nested()
228 /* Guest paging mode */ in set_dte_nested()
/linux/drivers/iommu/intel/
H A Dpasid.h30 * The PASID_FLAG_FL5LP flag Indicates using 5-level paging for first-
31 * level translation, otherwise, 4-level paging will be used.
284 * Setup the First Level Paging Mode field (Bit 130~131) of a
/linux/arch/powerpc/kvm/
H A Dbook3s_32_sr.S125 /* switch_mmu_context() needs paging, let's enable it */
141 /* Disable paging again */
H A Dbook3s_segment.S297 /* 1) enable paging for data */
299 ori r11, r9, MSR_DR /* Enable paging for data */
304 /* 3) disable paging again */
/linux/Documentation/userspace-api/
H A Diommufd.rst45 (i.e. a single struct iommu_domain) managed by the iommu driver. "PAGING"
156 | PFN storage | (paging) | |struct|
172 | PFN storage | (paging) | | (nested) | |struct|
194 | struct | | PFN | (paging) | | (nested) | |struct|

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