| /linux/drivers/gpu/drm/imagination/ |
| H A D | pvr_mmu.c | 1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
17 #include <linux/dma-mapping.h>
24 #define PVR_MASK_FROM_SIZE(size_) (~((size_) - U64_C(1)))
27 * The value of the device page size (%PVR_DEVICE_PAGE_SIZE) is currently
28 * pegged to the host page size (%PAGE_SIZE). This chunk of macro goodness both
29 * ensures that the selected host page size corresponds to a valid device page
57 # error Unsupported device page size PVR_DEVICE_PAGE_SIZE
62 (PVR_DEVICE_PAGE_SHIFT - PVR_SHIFT_FROM_SIZE(SZ_4K)))
65 PVR_MMU_SYNC_LEVEL_NONE = -1,
78 * pvr_mmu_set_flush_flags() - Set MMU cache flush flags for next call to
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| /linux/drivers/infiniband/hw/mthca/ |
| H A D | mthca_memfree.c | 16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
40 #include <asm/page.h>
61 } page[]; member
68 if (chunk->nsg > 0) in mthca_free_icm_pages()
69 dma_unmap_sg(&dev->pdev->dev, chunk->mem, chunk->npages, in mthca_free_icm_pages()
72 for (i = 0; i < chunk->npages; ++i) in mthca_free_icm_pages()
73 __free_pages(sg_page(&chunk->mem[i]), in mthca_free_icm_pages()
74 get_order(chunk->mem[i].length)); in mthca_free_icm_pages()
81 for (i = 0; i < chunk->npages; ++i) { in mthca_free_icm_coherent()
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| /linux/drivers/gpu/drm/xe/ |
| H A D | xe_pt_walk.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * DOC: GPU page-table tree walking.
9 * The utilities in this file are similar to the CPU page-table walk
11 * the various levels of a page-table tree with an unsigned integer rather
12 * than by name. 0 is the lowest level, and page-tables with level 0 can
17 * Each struct xe_ptw, regardless of level is referred to as a page table, and
18 * multiple page tables typically form a page table tree with page tables at
19 * intermediate levels being page directories pointing at page tables at lower
20 * levels. A shared page table for a given address range is a page-table which
24 * Please keep this code generic so that it can used as a drm-wide page-
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| H A D | xe_pt_walk.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
12 * struct xe_ptw - base class for driver pagetable subclassing.
16 * Drivers could subclass this, and if it's a page-directory, typically
25 * struct xe_pt_walk - Embeddable struct for walk parameters
31 * @shifts: Array of page-table entry shifts used for the
33 * page-shift as the first entry. It's legal for this pointer to be
51 * typedef xe_pt_entry_fn - gpu page-table-walk callback-function
52 * @parent: The parent page.table.
53 * @offset: The offset (number of entries) into the page table.
57 * @child: Pointer to pointer to child page-table at this @offset. The
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| /linux/Documentation/mm/ |
| H A D | mmu_notifier.rst | 1 When do you need to notify inside page table lock ?
6 the page table lock. But that notification is not necessary in all cases.
9 thing like ATS/PASID to get the IOMMU to walk the CPU page table to access a
11 those secondary TLB while holding page table lock when clearing a pte/pmd:
13 A) page backing address is free before mmu_notifier_invalidate_range_end()
14 B) a page table entry is updated to point to a new page (COW, write fault
15 on zero page, __replace_page(), ...)
18 a page that might now be used by some completely different task.
23 - take page table lock
24 - clear page table entry and notify ([pmd/pte]p_huge_clear_flush_notify())
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| H A D | multigen_lru.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Multi-Gen LRU
6 The multi-gen LRU is an alternative LRU implementation that optimizes
7 page reclaim and improves performance under memory pressure. Page
14 ----------
20 * Simple self-correcting heuristics
23 implementations. In the multi-gen LRU, each generation represents a
25 (time-based) common frame of reference and therefore help make better
30 accessed bit. A rmap walk targets a single page and does not try to
31 profit from discovering a young PTE. A page table walk can sweep all
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| H A D | swap-table.rst | 1 .. SPDX-License-Identifier: GPL-2.0
6 Swap Table
9 Swap table implements swap cache as a per-cluster swap cache value array.
12 ----------
14 A swap entry contains the information required to serve the anonymous page
20 The swap offset is the offset of the swap file to read the page data from.
23 ----------
36 out folio. This is the normal state for a swapped out page.
38 Swap Table Internals
39 --------------------
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| /linux/include/linux/ |
| H A D | io-pgtable.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
24 * struct iommu_flush_ops - IOMMU callbacks for TLB and page table management.
31 * single page. IOMMUs that cannot batch TLB invalidation
48 * struct io_pgtable_cfg - Configuration data for a set of page tables.
51 * action by the low-level page table allocator.
52 * @pgsize_bitmap: A bitmap of page sizes supported by this set of page
56 * @coherent_walk: A flag to indicate whether or not page table walks made
60 * page table walker.
66 * even in non-secure state where they should normally be ignored.
71 * format, and/or requires some format-specific default value.
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_gart.c | 43 * The GART (Graphics Aperture Remapping Table) is an aperture
46 * perspective. A page table maps the pages in the aperture
50 * and AGP. AGP works similarly, but the GART table is configured
62 * Common GART table functions.
66 * amdgpu_gart_dummy_page_init - init dummy page used by the driver
70 * Allocate the dummy page used by the driver (all asics).
71 * This dummy page is used by the driver as a filler for gart entries
73 * Returns 0 on sucess, -ENOMEM on failure.
77 struct page *dummy_page = ttm_glob.dummy_read_page; in amdgpu_gart_dummy_page_init()
79 if (adev->dummy_page_addr) in amdgpu_gart_dummy_page_init()
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| /linux/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/ |
| H A D | mmu.json | 45 "PublicDescrition": "Data-side S1 page walk cache lookup",
48 "BriefDescription": "Data-side S1 page walk cache lookup"
51 "PublicDescrition": "Data-side S1 page walk cache refill",
54 "BriefDescription": "Data-side S1 page walk cache refill"
57 "PublicDescrition": "Data-side S2 page walk cache lookup",
60 "BriefDescription": "Data-side S2 page walk cache lookup"
63 "PublicDescrition": "Data-side S2 page walk cache refill",
66 "BriefDescription": "Data-side S2 page walk cache refill"
69 "PublicDescription": "Data-side S1 table walk fault",
72 "BriefDescription": "Data-side S1 table walk fault"
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| /linux/tools/perf/pmu-events/arch/x86/amdzen4/ |
| H A D | memory.json | 5 …"BriefDescription": "Store-to-load conflicts (load unable to complete due to a non-forwardable con…
11 "BriefDescription": "Number of memory load operations dispatched to the load-store unit.",
17 "BriefDescription": "Number of memory store operations dispatched to the load-store unit.",
23 "BriefDescription": "Number of memory load-store operations dispatched to the load-store unit.",
29 "BriefDescription": "Store-to-load-forward (STLF) hits."
34 …"BriefDescription": "Non-cacheable store commits cancelled due to the non-cacheable commit buffer …
46 …"L1 DTLB misses with L2 DTLB hits for coalesced pages. A coalesced page is a 16k page created from…
64 …"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 4k pa…
70 …1 DTLB misses with L2 DTLB misses (page-table walks are requested) for coalesced pages. A coalesce…
76 …"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 2M pa…
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| /linux/include/asm-generic/ |
| H A D | pgalloc.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
11 * __pte_alloc_one_kernel - allocate memory for a PTE-level kernel page table
15 * anything beyond simple page allocation.
38 * pte_alloc_one_kernel - allocate memory for a PTE-level kernel page table
51 * pte_free_kernel - free PTE-level kernel page table memory
53 * @pte: pointer to the memory containing the page table
61 * __pte_alloc_one - allocate memory for a PTE-level user page table
65 * Allocate memory for a page table and ptdesc and runs pagetable_pte_ctor().
68 * anything beyond simple page allocation or must have custom GFP flags.
70 * Return: `struct page` referencing the ptdesc or %NULL on error
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| /linux/tools/perf/pmu-events/arch/powerpc/power9/ |
| H A D | marked.json | 10 …"BriefDescription": "A Page Directory Entry was reloaded to a level 1 page walk cache from beyond …
20 … Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same …
45 …"BriefDescription": "A Page Table Entry was reloaded to a level 3 page walk cache from the core's …
50 …"BriefDescription": "A Page Table Entry was reloaded to a level 3 page walk cache from the core's …
60 …iption": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a marke…
70 …Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the sa…
95 …Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the …
100 …Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the sa…
140 …"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the loc…
170 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without d…
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| H A D | pipeline.json | 10 "BriefDescription": "Number of I-ERAT reloads"
25 …"BriefDescription": "Finish stall because the NTF instruction was a multi-cycle instruction issued…
35 …Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Dist…
40 …iption": "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to …
80 …Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same…
95 …Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same…
110 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 4K"
115 …Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Me…
120 …"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 16G (hpt mode) and 1G (radi…
140 "BriefDescription": "IERAT Reloaded (Miss) for a 16M page"
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| H A D | translation.json | 20 "BriefDescription": "Double-Precion or Quad-Precision instruction completed"
25 …Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Dis…
35 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another …
60 …Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a di…
75 …"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data fro…
100 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same…
130 "BriefDescription": "Demand LD - L2 Miss (not L2 hit)"
140 …"BriefDescription": "The number a times the core transitioned from a stall to ICT-empty for this t…
145 …"BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L…
150 …"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data fro…
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| /linux/Documentation/driver-api/ |
| H A D | mtdnand.rst | 10 The generic NAND driver supports almost all NAND and AG-AND based chips
31 --------------------------
37 - [MTD Interface]
43 - [NAND Interface]
48 - [GENERIC]
53 - [DEFAULT]
65 -------------------------------
71 - [INTERN]
77 - [REPLACEABLE]
86 - [BOARDSPECIFIC]
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| H A D | generic_pt.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Generic Radix Page Table
7 .. kernel-doc:: include/linux/generic_pt/common.h
8 :doc: Generic Radix Page Table
10 .. kernel-doc:: drivers/iommu/generic_pt/pt_defs.h
11 :doc: Generic Page Table Language
16 Generic PT is structured as a multi-compilation system. Since each format
22 map/unmap, etc.) and the per-format code can be directly inlined into the
23 per-format compilation unit. For something like IOMMU each format will be
24 compiled into a per-format IOMMU operations kernel module.
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| /linux/drivers/hwtracing/coresight/ |
| H A D | coresight-catu.c | 1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/dma-mapping.h>
19 #include "coresight-catu.h"
20 #include "coresight-priv.h"
21 #include "coresight-tmc.h"
24 dev_get_drvdata(csdev->dev.parent)
26 /* Verbose output for CATU table contents */
39 * CATU uses a page size of 4KB for page tables as well as data pages.
40 * Each 64bit entry in the table has the following format.
43 * ------------------------------------
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| /linux/drivers/net/ethernet/mellanox/mlx4/ |
| H A D | icm.c | 15 * - Redistributions of source code must retain the above
19 * - Redistributions in binary form must reproduce the above
59 if (chunk->nsg > 0) in mlx4_free_icm_pages()
60 dma_unmap_sg(&dev->persist->pdev->dev, chunk->sg, chunk->npages, in mlx4_free_icm_pages()
63 for (i = 0; i < chunk->npages; ++i) in mlx4_free_icm_pages()
64 __free_pages(sg_page(&chunk->sg[i]), in mlx4_free_icm_pages()
65 get_order(chunk->sg[i].length)); in mlx4_free_icm_pages()
72 for (i = 0; i < chunk->npages; ++i) in mlx4_free_icm_coherent()
73 dma_free_coherent(&dev->persist->pdev->dev, in mlx4_free_icm_coherent()
74 chunk->buf[i].size, in mlx4_free_icm_coherent()
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| /linux/arch/x86/boot/compressed/ |
| H A D | ident_map_64.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * This code is used on x86_64 to create page table identity mappings on
4 * demand by building up a new set of page tables (or appending to the
7 * Copyright (C) 2015-2016 Yinghai Lu
37 /* Used to track our page table allocation area. */
45 * Allocates space for a page table entry, using struct alloc_pgt_data
54 /* Validate there is space available for a new page. */ in alloc_pgt_page()
55 if (pages->pgt_buf_offset >= pages->pgt_buf_size) { in alloc_pgt_page()
57 debug_putaddr(pages->pgt_buf_offset); in alloc_pgt_page()
58 debug_putaddr(pages->pgt_buf_size); in alloc_pgt_page()
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| /linux/Documentation/core-api/ |
| H A D | cachetlb.rst | 25 virtual-->physical address translations obtained from the software
26 page tables. Meaning that if the software page tables change, it is
28 Therefore when software page table changes occur, the kernel will
29 invoke one of the following flush methods _after_ the page table
35 any previous page table modification whatsoever will be
38 This is usually invoked when the kernel page tables are
45 any previous page table modifications for the address space
50 page table operations such as what happens during
58 interface must make sure that any previous page table
59 modifications for the address space 'vma->vm_mm' in the range
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| /linux/drivers/gpu/drm/vmwgfx/ |
| H A D | vmwgfx_mob.c | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT
4 * Copyright 2012-2023 VMware, Inc., Palo Alto, CA., USA
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
46 * struct vmw_mob - Structure containing page table and metadata for a
49 * @num_pages Number of pages that make up the page table.
50 * @pt_level The indirection level of the page table. 0-2.
51 * @pt_root_page DMA address of the level 0 page of the page table.
62 * struct vmw_otable - Guest Memory OBject table metadata
64 * @size: Size of the table (page-aligned).
65 * @page_table: Pointer to a struct vmw_mob holding the page table.
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| /linux/drivers/iommu/generic_pt/ |
| H A D | pt_common.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2024-2025, NVIDIA CORPORATION & AFFILIATES
17 * entry and can be called with a pts->index pointing to any sub item that makes
32 * pt_attr_from_entry() - Convert the permission bits back to attrs
44 * pt_can_have_leaf() - True if the current level can have an OA entry
53 * pt_can_have_table() - True if the current level can have a lower table
56 * Every level except 0 is allowed to have a lower table.
61 return pts->level > 0; in pt_can_have_table()
65 * pt_clear_entries() - Make entries empty (non-present)
66 * @pts: Starting table index
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| /linux/drivers/mtd/nand/raw/ |
| H A D | nand_bbt.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Bad block table support for the NAND driver
10 * When nand_scan_bbt is called, then it tries to find the bad block table
26 * For manufacturer created BBTs like the one found on M-SYS DOC devices
29 * The auto generated bad block table is located in the last good blocks
30 * of the device. The table is mirrored, so it can be updated eventually.
31 * The table is marked in the OOB area with an ident pattern and a version
38 * The table uses 2 bits per block
43 * The memory bad block table uses the following scheme:
52 * - bbts start at a page boundary, if autolocated on a block boundary
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| /linux/Documentation/virt/kvm/x86/ |
| H A D | mmu.rst | 1 .. SPDX-License-Identifier: GPL-2.0
13 - correctness:
18 - security:
21 - performance:
23 - scaling:
25 - hardware:
27 - integration:
29 so that swapping, page migration, page merging, transparent
31 - dirty tracking:
33 and framebuffer-based displays
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