Searched full:output_div (Results 1 – 2 of 2) sorted by relevance
38 struct regmap_field *output_div; member48 unsigned int input_div, output_div, loop_first, loop_second; in msc313_mpll_recalc_rate() local52 regmap_field_read(mpll->output_div, &output_div); in msc313_mpll_recalc_rate()58 output_rate /= max(output_div, 1U); in msc313_mpll_recalc_rate()97 mpll->output_div = devm_regmap_field_alloc(dev, regmap, config2_output_div_first); in msc313_mpll_probe()98 if (IS_ERR(mpll->output_div)) in msc313_mpll_probe()99 return PTR_ERR(mpll->output_div); in msc313_mpll_probe()
895 * is why it reduces down to be output_div. in zl3073x_dpll_output_pin_esync_get()949 * the output_div. To get the supported esync pulse width of 25% of the in zl3073x_dpll_output_pin_esync_set()950 * period the output_div can just be divided by 2. Note that this in zl3073x_dpll_output_pin_esync_set()951 * assumes that output_div is even, otherwise some resolution will be in zl3073x_dpll_output_pin_esync_set()