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/linux/Documentation/i2c/
H A Di2c-topology.rst6 than a straight-forward I2C bus with one adapter and one or more devices.
10 1. A mux may be needed on the bus to prevent address collisions.
25 I2C transfers, and all adapters with a parent are part of an "i2c-mux"
28 Depending of the particular mux driver, something happens when there is
29 an I2C transfer on one of its child adapters. The mux driver can
30 obviously operate a mux, but it can also do arbitration with an external
31 bus master or open a gate. The mux driver has two operations for this,
40 mux-locked or parent-locked muxes.
43 Mux-locked muxes
44 ----------------
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/linux/Documentation/devicetree/bindings/i2c/
H A Di2c-mux-gpmux.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-mux-gpmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: General Purpose I2C Bus Mux
10 - Peter Rosin <peda@axentia.se>
13 This binding describes an I2C bus multiplexer that uses a mux controller
14 from the mux subsystem to route the I2C signals.
16 .-----. .-----.
18 .------------. '-----' '-----'
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/linux/drivers/mux/
H A Dcore.c1 // SPDX-License-Identifier: GPL-2.0
10 #define pr_fmt(fmt) "mux-core: " fmt
19 #include <linux/mux/consumer.h>
20 #include <linux/mux/driver.h>
25 * The idle-as-is "state" is not an actual state that may be selected, it
32 * struct mux_state - Represents a mux controller state specific to a given
34 * @mux: Pointer to a mux controller.
35 * @state: State of the mux to be selected.
41 struct mux_control *mux; member
46 .name = "mux",
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/linux/arch/arm/boot/dts/microchip/
H A Dat91-natte.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * at91-natte.dts - Device Tree include file for the Natte board
11 mux: mux-controller { label
12 compatible = "gpio-mux";
13 #mux-control-cells = <0>;
15 mux-gpios = <&ioexp 0 GPIO_ACTIVE_HIGH>,
20 batntc-mux {
21 compatible = "io-channel-mux";
22 io-channels = <&adc 5>;
23 io-channel-names = "parent";
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/linux/drivers/media/i2c/
H A Dmax9286.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2017-2019 Jacopo Mondi
6 * Copyright (C) 2017-2019 Kieran Bingham
7 * Copyright (C) 2017-2019 Laurent Pinchart
8 * Copyright (C) 2017-2019 Niklas Söderlund
20 #include <linux/i2c-mux.h>
26 #include <media/v4l2-async.h>
27 #include <media/v4l2-ctrls.h>
28 #include <media/v4l2-device.h>
29 #include <media/v4l2-fwnode.h>
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/linux/drivers/spi/
H A Dspi-dw-bt1.c1 // SPDX-License-Identifier: GPL-2.0-only
9 // Baikal-T1 DW APB SPI and System Boot SPI driver
17 #include <linux/mux/consumer.h>
24 #include <linux/spi/spi-mem.h>
27 #include "spi-dw.h"
35 struct mux_control *mux; member
52 struct dw_spi_bt1 *dwsbt1 = to_dw_spi_bt1(desc->mem->spi->controller); in dw_spi_bt1_dirmap_create()
54 if (!dwsbt1->map || in dw_spi_bt1_dirmap_create()
55 !dwsbt1->dws.mem_ops.supports_op(desc->mem, &desc->info.op_tmpl)) in dw_spi_bt1_dirmap_create()
56 return -EOPNOTSUPP; in dw_spi_bt1_dirmap_create()
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/linux/Documentation/devicetree/bindings/dpll/
H A Ddpll-pin.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dpll/dpll-pin.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ivan Vecera <ivecera@redhat.com>
14 by a DPLL( Digital Phase-Locked Loop) device. The pin is identified by
26 connection-type:
29 enum: [ext, gnss, int, mux, synce]
31 esync-control:
39 supported-frequencies-hz:
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/linux/Documentation/devicetree/bindings/clock/
H A Dfsl,qoriq-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,qoriq-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
15 multiple phase locked loops (PLL) to create a variety of frequencies
24 --------------- -------------
36 - items:
37 - enum:
38 - fsl,p2041-clockgen
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/linux/drivers/mtd/nand/onenand/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
48 a One-Time Programmable Block memory area.
51 The OTP block can be read, programmed and locked using the same
55 OTP block is fully-guaranteed to be a valid block.
61 Since the device is equipped with two DataRAMs, and two-plane NAND
69 Mux: KFM2G16Q2M, KFN4G16Q2M,
/linux/drivers/clk/davinci/
H A Dda8xx-cfgchip.c1 // SPDX-License-Identifier: GPL-2.0
3 * Clock driver for DA8xx/AM17xx/AM18xx/OMAP-L13x CFGCHIP
8 #include <linux/clk-provider.h>
12 #include <linux/mfd/da8xx-cfgchip.h>
15 #include <linux/platform_data/clk-da8xx-cfgchip.h>
21 /* --- Gate clocks --- */
46 return regmap_write_bits(clk->regmap, clk->reg, clk->mask, clk->mask); in da8xx_cfgchip_gate_clk_enable()
53 regmap_write_bits(clk->regmap, clk->reg, clk->mask, 0); in da8xx_cfgchip_gate_clk_disable()
61 regmap_read(clk->regmap, clk->reg, &val); in da8xx_cfgchip_gate_clk_is_enabled()
63 return !!(val & clk->mask); in da8xx_cfgchip_gate_clk_is_enabled()
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/linux/net/kcm/
H A Dkcmsock.c1 // SPDX-License-Identifier: GPL-2.0-only
47 return (struct kcm_tx_msg *)skb->cb; in kcm_tx_msg()
52 csk->sk_err = EPIPE; in report_csk_error()
59 struct sock *csk = psock->sk; in kcm_abort_tx_psock()
60 struct kcm_mux *mux = psock->mux; in kcm_abort_tx_psock() local
64 spin_lock_bh(&mux->lock); in kcm_abort_tx_psock()
66 if (psock->tx_stopped) { in kcm_abort_tx_psock()
67 spin_unlock_bh(&mux->lock); in kcm_abort_tx_psock()
71 psock->tx_stopped = 1; in kcm_abort_tx_psock()
72 KCM_STATS_INCR(psock->stats.tx_aborts); in kcm_abort_tx_psock()
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/linux/sound/soc/codecs/
H A Dda7213.c1 // SPDX-License-Identifier: GPL-2.0-or-later
34 /* -54dB */
35 0x0, 0x11, TLV_DB_SCALE_ITEM(-5400, 0, 0),
36 /* -52.5dB to 15dB */
37 0x12, 0x3f, TLV_DB_SCALE_ITEM(-5250, 150, 0)
42 /* -7
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H A Dda7219.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * da7219.c - DA7219 ALSA SoC Codec Driver
13 #include <linux/clk-provider.h>
26 #include <sound/soc-dapm.h>
33 #include "da7219-aad.h"
41 static const DECLARE_TLV_DB_SCALE(da7219_mic_gain_tlv, -600, 600, 0);
42 static const DECLARE_TLV_DB_SCALE(da7219_mixin_gain_tlv, -450, 150, 0);
43 static const DECLARE_TLV_DB_SCALE(da7219_adc_dig_gain_tlv, -8325, 75, 0);
44 static const DECLARE_TLV_DB_SCALE(da7219_alc_threshold_tlv, -9450, 150, 0);
47 static const DECLARE_TLV_DB_SCALE(da7219_sidetone_gain_tlv, -4200, 300, 0);
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H A Dda7218.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * da7218.c - DA7218 ALSA SoC Codec Driver
22 #include <sound/soc-dapm.h>
37 static const DECLARE_TLV_DB_SCALE(da7218_mic_gain_tlv, -600, 600, 0);
38 static const DECLARE_TLV_DB_SCALE(da7218_mixin_gain_tlv, -450, 150, 0);
39 static const DECLARE_TLV_DB_SCALE(da7218_in_dig_gain_tlv, -8325, 75, 0);
40 static const DECLARE_TLV_DB_SCALE(da7218_ags_trigger_tlv, -9000, 600, 0);
42 static const DECLARE_TLV_DB_SCALE(da7218_alc_threshold_tlv, -9450, 150, 0);
47 static const DECLARE_TLV_DB_SCALE(da7218_dmix_gain_tlv, -4200, 150, 0);
50 static const DECLARE_TLV_DB_SCALE(da7218_dgs_trigger_tlv, -9450, 150, 0);
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H A Dwm8996.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * wm8996.c - WM8996 audio codec interface
5 * Copyright 2011-2 Wolfson Microelectronics PLC.
108 regcache_mark_dirty(wm8996->regmap); \
299 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0);
300 static const DECLARE_TLV_DB_SCALE(digital_tlv, -720
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/linux/drivers/media/dvb-frontends/
H A Dmxl692_defs.h1 /* SPDX-License-Identifier: GPL-2.0 */
23 #define MXL_EAGLE_VERSION_SIZE 5 /* A.B.C.D-RCx */
226 /* Enum of I/O Mux function, used in device I/O mux configuration API */
271 MXL_EAGLE_QAM_DEMOD_ANNEX_A, /* DVB-C */
295 MXL_EAGLE_OOB_DEMOD_SYMB_RATE_0_772MHZ, /* ANSI/SCTE 55-2 0.772 MHz */
296 MXL_EAGLE_OOB_DEMOD_SYMB_RATE_1_024MHZ, /* ANSI/SCTE 55-1 1.024 MHz */
297 MXL_EAGLE_OOB_DEMOD_SYMB_RATE_1_544MHZ, /* ANSI/SCTE 55-2 1.544 MHz */
509 u8 locked; member
/linux/sound/usb/
H A Dmixer_scarlett.c1 // SPDX-License-Identifier: GPL-2.0-or-later
21 * Auto-detection via UAC2 is not feasible to properly discover the vast
38 * - change Impedance of inputs (Line-in, Mic / Instrument, Hi-Z)
39 * - select clock source
40 * - dynamic input to mixer-matrix assignment
41 * - 18 x 6 mixer-matrix gain stages
42 * - bus routing & volume control
43 * - automatic re-initialization on connect if device was power-cycled
49 * pad (-10dB) switch, wValue=0x0b01 + channel, data=Off/On (2bytes)
54 * 0x29 Set Sample-rate, wValue=0x0100, data=sample-rate(4bytes)
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/linux/drivers/clk/xilinx/
H A Dxlnx_vcu.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016 - 2017 Xilinx, Inc.
11 #include <linux/clk-provider.h>
17 #include <linux/mfd/syscon/xlnx-vcu.h>
23 #include <dt-bindings/clock/xlnx-vcu.h>
51 * struct xvcu_device - Xilinx VCU init device structure
84 * struct xvcu_pll_cfg - Helper data
206 * xvcu_read - Read from the VCU register space
219 * xvcu_write - Write to the VCU register space
240 void __iomem *base = pll->reg_base; in xvcu_pll_wait_for_lock()
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/linux/drivers/pinctrl/intel/
H A Dpinctrl-intel.c1 // SPDX-License-Identifier: GPL-2.0
25 #include <linux/pinctrl/pinconf-generic.h>
29 #include <linux/platform_data/x86/pwm-lpss.h>
32 #include "pinctrl-intel.h"
92 * 0 0 0 -
127 #define pin_to_padno(c, p) ((p) - (c)->pin_base)
128 #define padgroup_offset(g, p) ((p) - (g)->base)
132 __ci < pctrl->ncommunities && (community = &pctrl->communities[__ci]); \
137 __gi < community->ngpps && (grp = &community->gpps[__gi]); \
146 if (grp->gpio_base == INTEL_GPIO_BASE_NOMAP) {} else
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/linux/drivers/clk/ti/
H A Dadpll.c1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <linux/clk-provider.h>
183 err = of_property_read_string_index(d->np, in ti_adpll_clk_get_name()
184 "clock-output-names", in ti_adpll_clk_get_name()
190 name = devm_kasprintf(d->dev, GFP_KERNEL, "%08lx.adpll.%s", in ti_adpll_clk_get_name()
191 d->pa, postfix); in ti_adpll_clk_get_name()
207 d->clocks[index].clk = clock; in ti_adpll_setup_clock()
208 d->clocks[index].unregister = unregister; in ti_adpll_setup_clock()
214 dev_warn(d->dev, "clock %s con_id lookup may fail\n", in ti_adpll_setup_clock()
216 snprintf(con_id, 16, "pll%03lx%s", d->pa & 0xfff, postfix + 1); in ti_adpll_setup_clock()
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/linux/arch/arm/boot/dts/ti/omap/
H A Dmotorola-mapphone-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
6 #include "motorola-cpcap-mapphone.dtsi"
10 * We seem to have only 1021 MB accessible, 1021 - 1022 is locked,
11 * then 1023 - 1024 seems to contain mbm.
19 gpio-poweroff {
20 compatible = "gpio-poweroff";
21 pinctrl-0 = <&poweroff_gpio>;
22 pinctrl-names = "default";
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/linux/drivers/net/mctp/
H A Dmctp-i2c.c1 // SPDX-License-Identifier: GPL-2.0
10 * mux topology a single I2C client is attached to the root of the mux topology,
11 * shared between all mux I2C busses underneath. For non-mux cases an I2C client
14 * mctp-i2c-controller.yml devicetree binding has further details.
23 #include <linux/i2c-mux.h>
31 #define MCTP_I2C_MAXMTU (MCTP_I2C_MAXBLOCK - 1)
41 #define MCTP_I2C_OF_PROP "mctp-controller"
87 * mux tree, shared by multiple netdevs
118 return i2c_root_adapter(&adap->dev); in mux_root_adapter()
120 /* In non-mux config all i2c adapters are root adapters */ in mux_root_adapter()
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/linux/sound/pci/ca0106/
H A Dca0106.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (c) 2004 James Courtier-Dutton <James@superbug.demon.co.uk>
50 * Implement support for Line-in capture on SB Live 24bit.
73 #define IPR_MIDI_RX_B 0x00020000 /* MIDI UART-B Receive buffer non-empty */
74 #define IPR_MIDI_TX_B 0x00010000 /* MIDI UART-B Transmit buffer empty */
87 #define IPR_MIDI_RX_A 0x00000004 /* MIDI UART-A Receive buffer non-empty */
88 #define IPR_MIDI_TX_A 0x00000002 /* MIDI UART-A Transmit buffer empty */
93 #define INTE_MIDI_RX_B 0x00020000 /* MIDI UART-B Receive buffer non-empty */
94 #define INTE_MIDI_TX_B 0x00010000 /* MIDI UART-B Transmit buffer empty */
107 #define INTE_MIDI_RX_A 0x00000004 /* MIDI UART-A Receive buffer non-empty */
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/linux/drivers/pinctrl/renesas/
H A Dpinctrl-rzn1.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014-2018 Renesas Electronics Europe Limited
9 #include <dt-bindings/pinctrl/rzn1-pinctrl.h>
19 #include <linux/pinctrl/pinconf-generic.h>
26 #include "../pinctrl-utils.h"
70 * Both the Level 1 mux registers and Level 2 mux registers have the same
78 /* MDIO mux registers, level2 only */
83 * struct rzn1_pmx_func - describes rzn1 pinmux functions
95 * struct rzn1_pin_group - describes an rzn1 pin group
101 * @pin_ids: array of pin_ids, i.e. the value used to select the mux
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/linux/drivers/dma/
H A Damba-pl08x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (c) 2010 ST-Ericsson SA
27 * - CH_CONFIG register at different offset,
28 * - separate CH_CONTROL2 register for transfer size,
29 * - bigger maximum transfer size,
30 * - 8-word aligned LLI, instead of 4-word, due to extra CCTL2 word,
31 * - no support for peripheral flow control.
45 * (Bursts are irrelevant for mem to mem transfers - there are no burst
51 * - DMAC flow control: the transfer size defines the number of transfers
58 * - Peripheral flow control: the transfer size is ignored (and should be
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