Searched +full:mt8195 +full:- +full:dsp (Results 1 – 8 of 8) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/dsp/mediatek,mt8195-dsp.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Mediatek mt8195 DSP core10 - YC Hung <yc.hung@mediatek.com>13 Some boards from mt8195 contain a DSP core used for14 advanced pre- and post- audio processing.18 const: mediatek,mt8195-dsp22 - description: Address and size of the DSP Cfg registers[all …]
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)9 * Hardware interface for audio DSP on mt819523 #include "../../sof-of-dev.h"25 #include "../mtk-adsp-common.h"26 #include "mt8195.h"27 #include "mt8195-clk.h"48 struct device *dev = &pdev->dev; in platform_parse_resource()58 ret = of_reserved_mem_region_to_resource(dev->of_node, 1, &res); in platform_parse_resource()64 adsp->pa_dram = (phys_addr_t)res.start; in platform_parse_resource()65 adsp->dramsize = resource_size(&res); in platform_parse_resource()[all …]
1 /* SPDX-License-Identifier: GPL-2.0 */6 * Header file for the mt8195 DSP register definition114 /* dsp wdt */117 /* dsp mbox */127 /*dsp sys ao*/132 /* DSP memories */148 #define SRAM_PHYS_BASE_FROM_DSP_VIEW 0x40000000 /* MT8195 DSP view */149 #define DRAM_PHYS_BASE_FROM_DSP_VIEW 0x60000000 /* MT8195 DSP view */151 /*remap dram between AP and DSP view, 4KB aligned*/153 #define DRAM_REMAP_MASK (BIT(DRAM_REMAP_SHIFT) - 1)[all …]
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)7 // Hardware interface for mt8195 DSP code loader10 #include "mt8195.h"32 /* delay 10 DSP cycles at 26M about 1us by IP vendor's suggestion */ in sof_hifixdsp_boot_sequence()
1 /* SPDX-License-Identifier: GPL-2.0 */6 * Header file for the mt8195 DSP clock definition14 /*DSP clock*/
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)22 This option is not user-selectable but automagically handled by26 tristate "SOF support for MT8186 audio DSP"36 tristate "SOF support for MT8195 audio DSP"41 using the mt8195 processors.
1 # SPDX-License-Identifier: GPL-2.0-only397 to PCI-E and USB.427 to PCI-E and USB.912 bool "Clock driver for MediaTek MT8195"918 This driver supports MediaTek MT8195 clocks.921 tristate "Clock driver for MediaTek MT8195 apusys"925 This driver supports MediaTek MT8195 AI Processor Unit System clocks.928 tristate "Clock driver for MediaTek MT8195 imp_iic_wrap"932 This driver supports MediaTek MT8195 I2C/I3C clocks.935 tristate "Clock driver for MediaTek MT8195 mfgcfg"[all …]
1 // SPDX-License-Identifier: GPL-2.03 * mt8195-mt6359.c --4 * MT8195-MT6359 ALSA SoC machine driver code22 #include "../common/mtk-af[all...]