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/linux/arch/powerpc/sysdev/
H A Dfsl_msi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2007-2011 Freescale Semiconductor, Inc.
11 #include <linux/msi.h>
24 #include <asm/ppc-pci.h>
39 #define msi_hwirq(msi, msir_index, intr_index) \ argument
40 ((msir_index) << (msi)->srs_shift | \
41 ((intr_index) << (msi)->ibs_shift))
47 u32 msiir_offset; /* Offset of MSIIR, relative to start of MSIR bank */
63 * in the cascade interrupt. So, this MSI interrupt has been acked
71 struct fsl_msi *msi_data = irqd->domain->host_data; in fsl_msi_print_chip()
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H A Dmsi_bitmap.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2006-2008, Michael Ellerman, IBM Corporation.
18 int offset, order = get_count_order(num); in msi_bitmap_alloc_hwirqs() local
20 spin_lock_irqsave(&bmp->lock, flags); in msi_bitmap_alloc_hwirqs()
22 offset = bitmap_find_next_zero_area(bmp->bitmap, bmp->irq_count, 0, in msi_bitmap_alloc_hwirqs()
23 num, (1 << order) - 1); in msi_bitmap_alloc_hwirqs()
24 if (offset >= bmp->irq_count) in msi_bitmap_alloc_hwirqs()
27 bitmap_set(bmp->bitmap, offset, num); in msi_bitmap_alloc_hwirqs()
28 spin_unlock_irqrestore(&bmp->lock, flags); in msi_bitmap_alloc_hwirqs()
30 pr_debug("msi_bitmap: allocated 0x%x at offset 0x%x\n", num, offset); in msi_bitmap_alloc_hwirqs()
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/linux/Documentation/PCI/endpoint/
H A Dpci-ntb-function.rst1 .. SPDX-License-Identifier: GPL-2.0
9 PCI Non-Transparent Bridges (NTB) allow two host systems to communicate
26 .. code-block:: text
28 +-------------+ +-------------+
32 +------^------+ +------^------+
35 +---------|-------------------------------------------------|---------+
36 | +------v------+ +------v------+ |
40 | | <-----------------------------------> | |
45 | +-------------+ +-------------+ |
46 +---------------------------------------------------------------------+
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/linux/include/linux/
H A Dpci-epc.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 #include <linux/pci-epf.h>
17 UNKNOWN_INTERFACE = -1,
36 * struct pci_epc_map - information about EPC memory for mapping a RC PCI
65 * enum pci_epc_aux_resource_type - auxiliary resource type identifiers
78 * struct pci_epc_aux_resource - a physical auxiliary resource that may be
85 * @bar_offset: offset within @bar where the resource starts (valid iff
87 * @u: type-specific metadata
106 * struct pci_epc_ops - set of function pointers for performing EPC operations
110 * @align_addr: operation to get the mapping address, mapping size and offset
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H A Dpci-epf.h1 /* SPDX-License-Identifier: GPL-2.0 */
14 #include <linux/device-id/pci.h>
15 #include <linux/msi.h>
23 NO_BAR = -1,
33 * struct pci_epf_header - represents standard configuration header
36 * @revid: specifies a device-specific revision identifier
37 * @progif_code: identifies a specific register-level programming interface
41 * @subsys_vendor_id: vendor of the add-in card or subsystem
59 * struct pci_epf_ops - set of function pointers for performing EPF operations
63 * @add_cfs: ops to initialize function-specific configfs attributes
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/linux/drivers/irqchip/
H A Dirq-gic-v2m.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * ARM GIC v2m MSI(-X) support
21 #include <linux/msi.h>
26 #include <linux/irqchip/arm-gic.h>
27 #include <linux/irqchip/arm-gic-common.h>
29 #include <linux/irqchip/irq-msi-lib.h>
34 * [25:16] lowest SPI assigned to MSI
36 * [9:0] Numer of SPIs assigned to MSI
52 /* APM X-Gene with GICv2m MSI_IIDR register value */
72 u32 spi_offset; /* offset to be subtracted from SPI number */
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H A Dirq-bcm2712-mip.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/msi.h>
14 #include <linux/irqchip/irq-msi-lib.h>
30 * struct mip_priv - MSI-X interrupt controller data
33 * @msg_addr: PCIe MSI-X address
34 * @msi_base: MSI base
36 * @msi_offset: MSI offset
57 msg->address_hi = upper_32_bits(mip->msg_addr); in mip_compose_msi_msg()
58 msg->address_lo = lower_32_bits(mip->msg_addr); in mip_compose_msi_msg()
59 msg->data = d->hwirq; in mip_compose_msi_msg()
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/linux/drivers/xen/xen-pciback/
H A Dconf_space_capability.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Backend - Handles the virtual fields found on the capability lists
26 .offset = PCI_CAP_LIST_ID,
36 list_add_tail(&cap->cap_list, &capabilities); in register_capability()
46 cap_offset = pci_find_capability(dev, cap->capability); in xen_pcibk_config_capability_add_fields()
48 dev_dbg(&dev->dev, "Found capability 0x%x at 0x%x\n", in xen_pcibk_config_capability_add_fields()
49 cap->capability, cap_offset); in xen_pcibk_config_capability_add_fields()
57 cap->fields, in xen_pcibk_config_capability_add_fields()
68 static int vpd_address_write(struct pci_dev *dev, int offset, u16 value, in vpd_address_write() argument
75 return pci_write_config_word(dev, offset, value); in vpd_address_write()
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/linux/drivers/pci/controller/
H A Dpcie-iproc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
9 #include <linux/pci-ecam.h>
10 #include <linux/msi.h>
17 #include <linux/irqchip/arm-gic-v3.h>
25 #include "pcie-iproc.h"
92 * struct iproc_pcie_ob_map - iProc PCIe outbound mapping controller-specific
139 * enum iproc_pcie_ib_map_type - iProc PCIe inbound mapping type
151 * struct iproc_pcie_ib_map - iProc PCIe inbound mapping controller-specific
160 * @imap_addr_offset: register offset between the upper and lower 32-bit
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H A Dpcie-rockchip-ep.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Simon Xue <xxm@rock-chips.com>
18 #include <linux/pci-epc.h>
20 #include <linux/pci-epf.h>
24 #include "pcie-rockchip.h"
27 * struct rockchip_pcie_ep - private data for PCIe endpoint controller driver
33 * @irq_phys_addr: base address on the AXI bus where the MSI/INTX IRQ
36 * the sending of a memory write (MSI) / normal message (INTX
38 * @irq_pci_addr: used to save the current mapping of the MSI/INTX IRQ
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/linux/drivers/net/ethernet/microsoft/mana/
H A Dgdma_main.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
11 #include <linux/msi.h>
35 static u32 mana_gd_r32(struct gdma_context *g, u64 offset) in mana_gd_r32() argument
37 return readl(g->bar0_va + offset); in mana_gd_r32()
40 static u64 mana_gd_r64(struct gdma_context *g, u64 offset) in mana_gd_r64() argument
42 return readq(g->bar0_va + offset); in mana_gd_r64()
52 gc->db_page_size = mana_gd_r32(gc, GDMA_PF_REG_DB_PAGE_SIZE) & 0xFFFF; in mana_gd_init_pf_regs()
58 if (gc->db_page_size < SZ_4K) { in mana_gd_init_pf_regs()
59 dev_err(gc->dev, in mana_gd_init_pf_regs()
61 gc->db_page_size, SZ_4K); in mana_gd_init_pf_regs()
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/linux/Documentation/misc-devices/
H A Dspear-pcie-gadget.rst1 .. SPDX-License-Identifier: GPL-2.0
37 -----------------------
42 no_of_msi zero if MSI is not enabled by host. A positive value is the
43 number of MSI vector granted.
48 bar0_rw_offset returns offset of bar0 for which bar0_data will return value.
53 ------------------------
58 INTA, MSI or NO_INT). Select MSI only when you have programmed
60 no_of_msi number of MSI vector needed.
61 inta write 1 to assert INTA and 0 to de-assert.
62 send_msi write MSI vector to be sent.
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/linux/drivers/bluetooth/
H A Dbtintel_pcie.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
55 /* Registers for MSI-X */
109 * Host-Device interface is active
110 * Host-Device interface is inactive(as reflected by IPC_SLEEP_CONTROL_CSR_AD)
111 * Host-Device interface is inactive(as reflected by IPC_SLEEP_CONTROL_CSR_AD)
158 /* Minimum and Maximum number of MSI-X Vector
204 * All members are write-only for host and read-only for device.
229 * @tr_msi_vec: Transfer Ring MSI-X Vector
230 * @cr_msi_vec: Completion Ring MSI-X Vector
448 * @irq_lock: spinlock for MSI-X
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/linux/drivers/pci/controller/plda/
H A Dpcie-microchip-host.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2018 - 2020 Microchip Corporation. All rights reserved.
18 #include <linux/msi.h>
21 #include <linux/pci-ecam.h>
26 #include "../pci-host-common.h"
27 #include "pcie-plda.h"
88 /* PCIe Config space MSI capability structure */
136 .offset = PCIE_EVENT_INT, \
143 .offset = SEC_ERROR_INT, \
150 .offset = DED_ERROR_INT, \
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/linux/drivers/net/wireless/ath/ath11k/
H A Dpci.c1 // SPDX-License-Identifier: BSD-3-Clause-Clear
3 * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved.
8 #include <linux/msi.h>
49 return mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev); in ath11k_pci_bus_wake_up()
56 mhi_device_put(ab_pci->mhi_ctrl->mhi_dev); in ath11k_pci_bus_release()
59 static u32 ath11k_pci_get_window_start(struct ath11k_base *ab, u32 offset) in ath11k_pci_get_window_start() argument
61 if (!ab->hw_params.static_window_map) in ath11k_pci_get_window_start()
64 if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < ATH11K_PCI_WINDOW_RANGE_MASK) in ath11k_pci_get_window_start()
65 /* if offset lies within DP register range, use 3rd window */ in ath11k_pci_get_window_start()
67 else if ((offset ^ HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab)) < in ath11k_pci_get_window_start()
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/linux/Documentation/devicetree/bindings/powerpc/4xx/
H A Dhsta.txt10 Currently only the MSI support is used by Linux using the following
14 - compatible : "ibm,476gtr-hsta-msi", "ibm,hsta-msi"
15 - reg : register mapping for the HSTA MSI space
16 - interrupts : ordered interrupt mapping for each MSI in the register
18 register offset of 0x00, the second to 0x10, etc.
/linux/arch/loongarch/kvm/intc/
H A Dpch_pic.c1 // SPDX-License-Identifier: GPL-2.0
22 if (mask & s->irr & ~s->mask) { in pch_pic_update_irq()
23 s->isr |= mask; in pch_pic_update_irq()
24 irq = s->htmsi_vector[irq]; in pch_pic_update_irq()
25 eiointc_set_irq(s->kvm->arch.eiointc, irq, level); in pch_pic_update_irq()
28 if (mask & s->isr & ~s->irr) { in pch_pic_update_irq()
29 s->isr &= ~mask; in pch_pic_update_irq()
30 irq = s->htmsi_vector[irq]; in pch_pic_update_irq()
31 eiointc_set_irq(s->kvm->arch.eiointc, irq, level); in pch_pic_update_irq()
51 spin_lock(&s->lock); in pch_pic_set_irq()
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/linux/drivers/iommu/iommufd/
H A Ddriver.c1 // SPDX-License-Identifier: GPL-2.0-only
6 /* Driver should use a per-structure helper in include/linux/iommufd.h */
12 return -EINVAL; in _iommufd_object_depend()
14 if (obj_dependent->type != obj_depended->type) in _iommufd_object_depend()
15 return -EINVAL; in _iommufd_object_depend()
17 refcount_inc(&obj_depended->users); in _iommufd_object_depend()
22 /* Driver should use a per-structure helper in include/linux/iommufd.h */
27 obj_dependent->type != obj_depended->type)) in _iommufd_object_undepend()
30 refcount_dec(&obj_depended->users); in _iommufd_object_undepend()
35 * Allocate an @offset to return to user space to use for an mmap() syscall
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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dfsl,mpic-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,mpic-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale MSI interrupt controller
10 The Freescale hypervisor and msi-address-64
11 -------------------------------------------
14 Freescale MSI driver calculates the address of MSIIR (in the MSI register
15 block) and sets that address as the MSI message address.
39 this. The address specified in the msi-address-64 property is the PCI
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/linux/arch/um/drivers/
H A Dvirt-pci.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/irqchip/irq-msi-lib.h>
12 #include <linux/msi.h>
16 #include "virt-pci.h"
35 static unsigned long um_pci_cfgspace_read(void *priv, unsigned int offset, in um_pci_cfgspace_read() argument
39 struct um_pci_device *dev = reg->dev; in um_pci_cfgspace_read()
57 return dev->ops->cfgspace_read(dev, offset, size); in um_pci_cfgspace_read()
60 static void um_pci_cfgspace_write(void *priv, unsigned int offset, int size, in um_pci_cfgspace_write() argument
64 struct um_pci_device *dev = reg->dev; in um_pci_cfgspace_write()
82 dev->ops->cfgspace_write(dev, offset, size, val); in um_pci_cfgspace_write()
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/linux/arch/powerpc/boot/dts/fsl/
H A Dqoriq-mpic.dtsi2 * QorIQ MPIC device tree stub [ controller @ offset 0x40000 ]
36 interrupt-controller;
37 #address-cells = <0>;
38 #interrupt-cells = <4>;
40 compatible = "fsl,mpic", "chrp,open-pic";
41 device_type = "open-pic";
42 clock-frequency = <0x0>;
46 compatible = "fsl,mpic-global-timer";
54 msi0: msi@41600 {
55 compatible = "fsl,mpic-msi";
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/linux/arch/arm64/boot/dts/marvell/
H A Darmada-ap80x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <2>;
25 compatible = "arm,psci-0.2";
29 reserved-memory {
30 #address-cells = <2>;
31 #size-cells = <2>;
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/linux/drivers/net/ethernet/netronome/nfp/
H A Dnfp_net_ctrl.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2 /* Copyright (C) 2015-2018 Netronome Systems, Inc. */
17 /* 64-bit per app capabilities */
23 * THB-350, 32k needs to be reserved.
27 /* Offset in Freelist buffer where packet starts on RX */
61 /* Hash type pre-pended when a RSS hash was computed */
80 /* Read/Write config words (0x0000 - 0x002c)
87 * %NFP_NET_CFG_EXN: MSI-X table entry for exceptions
88 * %NFP_NET_CFG_LSC: MSI-X table entry for link state changes
92 * - define Error details in UPDATE
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/linux/drivers/scsi/csiostor/
H A Dcsio_hw_t5.c4 * Copyright (c) 2008-2013 Chelsio Communications, Inc. All rights reserved.
15 * - Redistributions of source code must retain the above
19 * - Redistributions in binary form must reproduce the above
42 * Truncation intentional: we only read the bottom 32-bits of the in csio_t5_set_mem_win()
43 * 64-bit BAR0/BAR1 ... We use the hardware backdoor mechanism to in csio_t5_set_mem_win()
46 * accesses to our Configuration Space and we need to set up the PCI-E in csio_t5_set_mem_win()
48 * coming across the PCI-E link. in csio_t5_set_mem_win()
51 /* For T5, only relative offset inside the PCIe BAR is passed */ in csio_t5_set_mem_win()
60 WINDOW_V(ilog2(MEMWIN_APERTURE) - 10), in csio_t5_set_mem_win()
76 -1, 1 }, in csio_t5_pcie_intr_handler()
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/linux/drivers/crypto/cavium/nitrox/
H A Dnitrox_dev.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <linux/dma-mapping.h>
19 * struct nitrox_cmdq - NITROX command queue
68 * struct nitrox_hw - NITROX hardware information
69 * @partname: partname ex: CNN55xxx-xxx
120 * mbox_msg - Mailbox message data
149 * nitrox_vfdev - NITROX VF device instance in PF
167 * struct nitrox_iov - SR-IOV information
172 * @msix: MSI-X entry for PF in SR-IOV case
207 #define DEV(ndev) ((struct device *)(&(ndev)->pdev->dev))
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