Searched +full:msi +full:- +full:num +full:- +full:spis (Results 1 – 8 of 8) sorted by relevance
/linux/Documentation/devicetree/bindings/interrupt-controller/ |
H A D | al,alpine-msix.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/interrupt-controller/al,alpine-msix.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Antoine Tenart <atenart@kernel.org> 14 const: al,alpine-msix 19 interrupt-parent: true 21 msi-controller: true 23 al,msi-base-spi: 24 description: SPI base of the MSI frame [all …]
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/linux/arch/arm64/boot/dts/broadcom/northstar2/ |
H A D | ns2.dtsi | 35 #include <dt-bindings/interrupt-controller/arm-gic.h> 36 #include <dt-bindings/clock/bcm-ns2.h> 40 interrupt-parent = <&gic>; 41 #address-cells = <2>; 42 #size-cells = <2>; 45 #address-cells = <2>; 46 #size-cells = <0>; 50 compatible = "arm,cortex-a57"; 52 enable-method = "psci"; 53 next-level-cache = <&CLUSTER0_L2>; [all …]
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/linux/drivers/irqchip/ |
H A D | irq-gic-v2m.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * ARM GIC v2m MSI(-X) support 21 #include <linux/msi.h> 26 #include <linux/irqchip/arm-gic.h> 27 #include <linux/irqchip/arm-gic-common.h> 29 #include <linux/irqchip/irq-msi-lib.h> 34 * [25:16] lowest SPI assigned to MSI 36 * [9:0] Numer of SPIs assigned to MSI 52 /* APM X-Gene with GICv2m MSI_IIDR register value */ 71 u32 nr_spis; /* The number of SPIs for MSIs */ [all …]
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H A D | irq-alpine-msi.c | 6 * Antoine Tenart <antoine.tenart@free-electrons.com> 16 #include <linux/irqchip/arm-gic.h> 17 #include <linux/irqchip/irq-msi-lib.h> 18 #include <linux/msi.h> 27 #include <asm/msi.h> 44 guard(spinlock)(&priv->msi_map_lock); in alpine_msix_allocate_sgi() 45 first = bitmap_find_next_zero_area(priv->msi_map, priv->num_spis, 0, num_req, 0); in alpine_msix_allocate_sgi() 46 if (first >= priv->num_spis) in alpine_msix_allocate_sgi() 47 return -ENOSPC; in alpine_msix_allocate_sgi() 49 bitmap_set(priv->msi_map, first, num_req); in alpine_msix_allocate_sgi() [all …]
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/linux/arch/arm64/boot/dts/marvell/ |
H A D | armada-ap80x.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/thermal/thermal.h> 11 /dts-v1/; 14 #address-cells = <2>; 15 #size-cells = <2>; 25 compatible = "arm,psci-0.2"; 29 reserved-memory { 30 #address-cells = <2>; 31 #size-cells = <2>; [all …]
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/linux/arch/arm/boot/dts/amazon/ |
H A D | alpine.dtsi | 27 #include <dt-bindings/interrupt-controller/arm-gic.h> 30 #address-cells = <2>; 31 #size-cells = <2>; 42 #address-cells = <1>; 43 #size-cells = <0>; 44 enable-method = "al,alpine-smp"; 47 compatible = "arm,cortex-a15"; 50 clock-frequency = <1700000000>; 54 compatible = "arm,cortex-a15"; 57 clock-frequency = <1700000000>; [all …]
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/linux/arch/arm64/boot/dts/amazon/ |
H A D | alpine-v2.dtsi | 4 * Antoine Tenart <antoine.tenart@free-electrons.com> 16 * - Redistributions of source code must retain the above 20 * - Redistributions in binary form must reproduce the above 35 /dts-v1/; 37 #include <dt-bindings/interrupt-controller/arm-gic.h> 41 compatible = "al,alpine-v2"; 42 interrupt-parent = <&gic>; 43 #address-cells = <2>; 44 #size-cells = <2>; 47 #address-cells = <2>; [all …]
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H A D | alpine-v3.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 6 /dts-v1/; 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 12 compatible = "amazon,al-alpine-v3"; 14 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 20 #address-cells = <1>; 21 #size-cells = <0>; 25 compatible = "arm,cortex-a72"; [all …]
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