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/linux/drivers/comedi/drivers/
H A Dcb_das16_cs.c112 unsigned short misc2; member
161 devpriv->misc2 &= ~(DAS16CS_MISC2_BME | DAS16CS_MISC2_AI_GAIN_MASK); in das16cs_ai_insn_read()
164 devpriv->misc2 |= DAS16CS_MISC2_AI_GAIN_1; in das16cs_ai_insn_read()
167 devpriv->misc2 |= DAS16CS_MISC2_AI_GAIN_2; in das16cs_ai_insn_read()
170 devpriv->misc2 |= DAS16CS_MISC2_AI_GAIN_4; in das16cs_ai_insn_read()
173 devpriv->misc2 |= DAS16CS_MISC2_AI_GAIN_8; in das16cs_ai_insn_read()
176 outw(devpriv->misc2, dev->iobase + DAS16CS_MISC2_REG); in das16cs_ai_insn_read()
275 devpriv->misc2 |= DAS16CS_MISC2_UDIR; in das16cs_dio_insn_config()
277 devpriv->misc2 &= ~DAS16CS_MISC2_UDIR; in das16cs_dio_insn_config()
279 devpriv->misc2 |= DAS16CS_MISC2_LDIR; in das16cs_dio_insn_config()
[all …]
H A Ds626.h283 #define S626_LP_WRMISC2 0x0090 /* Write Misc2. */
284 #define S626_LP_RDMISC2 0x0082 /* Read Misc2. */
288 * enab writes to MISC2 (except Clear
291 #define S626_MISC1_WDISABLE 0x0000 /* Disable writes to MISC2. */
304 /* Bit masks for MISC2 register writes. */
308 /* Bit masks for MISC2 register that are the same for reads and writes. */
/linux/drivers/net/ethernet/mellanox/mlx5/core/steering/sws/
H A Ddr_ste_v1.c1439 struct mlx5dr_match_misc2 *misc2 = &value->misc2; in dr_ste_v1_build_mpls_tag() local
1442 DR_STE_SET_MPLS(mpls_v1, misc2, inner, tag); in dr_ste_v1_build_mpls_tag()
1444 DR_STE_SET_MPLS(mpls_v1, misc2, outer, tag); in dr_ste_v1_build_mpls_tag()
1490 struct mlx5dr_match_misc2 *misc2 = &value->misc2; in dr_ste_v1_build_tnl_mpls_tag() local
1492 if (DR_STE_IS_OUTER_MPLS_OVER_GRE_SET(misc2)) { in dr_ste_v1_build_tnl_mpls_tag()
1494 misc2, outer_first_mpls_over_gre_label); in dr_ste_v1_build_tnl_mpls_tag()
1497 misc2, outer_first_mpls_over_gre_exp); in dr_ste_v1_build_tnl_mpls_tag()
1500 misc2, outer_first_mpls_over_gre_s_bos); in dr_ste_v1_build_tnl_mpls_tag()
1503 misc2, outer_first_mpls_over_gre_ttl); in dr_ste_v1_build_tnl_mpls_tag()
1506 misc2, outer_first_mpls_over_udp_label); in dr_ste_v1_build_tnl_mpls_tag()
[all …]
H A Ddr_matcher.c296 static bool dr_mask_is_wqe_metadata_set(struct mlx5dr_match_misc2 *misc2) in dr_mask_is_wqe_metadata_set() argument
298 return misc2->metadata_reg_a; in dr_mask_is_wqe_metadata_set()
301 static bool dr_mask_is_reg_c_0_3_set(struct mlx5dr_match_misc2 *misc2) in dr_mask_is_reg_c_0_3_set() argument
303 return (misc2->metadata_reg_c_0 || misc2->metadata_reg_c_1 || in dr_mask_is_reg_c_0_3_set()
304 misc2->metadata_reg_c_2 || misc2->metadata_reg_c_3); in dr_mask_is_reg_c_0_3_set()
307 static bool dr_mask_is_reg_c_4_7_set(struct mlx5dr_match_misc2 *misc2) in dr_mask_is_reg_c_4_7_set() argument
309 return (misc2->metadata_reg_c_4 || misc2->metadata_reg_c_5 || in dr_mask_is_reg_c_4_7_set()
310 misc2->metadata_reg_c_6 || misc2->metadata_reg_c_7); in dr_mask_is_reg_c_4_7_set()
362 return DR_MASK_IS_OUTER_MPLS_OVER_GRE_SET(&mask->misc2) && in dr_mask_is_tnl_mpls_over_gre()
374 return DR_MASK_IS_OUTER_MPLS_OVER_UDP_SET(&mask->misc2) && in dr_mask_is_tnl_mpls_over_udp()
[all …]
H A Ddr_rule.c980 s_idx = offsetof(struct mlx5dr_match_param, misc2); in dr_rule_verify()
981 e_idx = min(s_idx + sizeof(param->misc2), value_size); in dr_rule_verify()
984 mlx5dr_err(matcher->tbl->dmn, "Rule misc2 parameters contains a value not specified by mask\n"); in dr_rule_verify()
H A Ddr_dbg.c652 dr_dump_hex_print(dump, (char *)&mask->misc2, sizeof(mask->misc2)); in dr_dump_matcher_mask()
/linux/drivers/soc/tegra/
H A Dari-tegra186.c50 u64 addr, misc1, misc2; in tegra186_ari_panic_handler() local
57 MCA_ARI_RW_SUBIDX_MSC2, 0, &misc2); in tegra186_ari_panic_handler()
62 bank_names[i], status, addr, misc1, misc2); in tegra186_ari_panic_handler()
/linux/drivers/net/ethernet/mellanox/mlx5/core/en/tc/
H A Dpost_meter.c85 void *misc2, *match_criteria; in mlx5e_post_meter_rate_fg_create() local
97 misc2 = MLX5_ADDR_OF(fte_match_param, match_criteria, misc_parameters_2); in mlx5e_post_meter_rate_fg_create()
98 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_5, MLX5_PACKET_COLOR_MASK); in mlx5e_post_meter_rate_fg_create()
/linux/drivers/gpu/drm/radeon/
H A Dradeon_atombios.c2043 u32 misc, u32 misc2) in radeon_atombios_parse_misc_flags_1_3() argument
2046 rdev->pm.power_state[state_index].misc2 = misc2; in radeon_atombios_parse_misc_flags_1_3()
2066 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE) in radeon_atombios_parse_misc_flags_1_3()
2084 u32 misc, misc2 = 0; in radeon_atombios_parse_power_table_1_3() local
2183 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2); in radeon_atombios_parse_power_table_1_3()
2204 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2); in radeon_atombios_parse_power_table_1_3()
2219 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2); in radeon_atombios_parse_power_table_1_3()
2238 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) { in radeon_atombios_parse_power_table_1_3()
2246 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2); in radeon_atombios_parse_power_table_1_3()
2268 rdev->pm.power_state[state_index - 1].misc2 = 0; in radeon_atombios_parse_power_table_1_3()
[all …]
/linux/drivers/fsi/
H A Dcf-fsi-fw.h130 /* Misc2 */
/linux/drivers/media/pci/tw686x/
H A Dtw686x-regs.h101 #define MISC2 VDREG2(0x196) macro
/linux/arch/mips/include/asm/sibyte/
H A Dbcm1480_l2c.h147 * L2 Misc2 Value Register (Table 60)
/linux/drivers/net/ethernet/mellanox/mlx5/core/
H A Deswitch_offloads.c111 void *misc2; in mlx5_eswitch_clear_rule_source_port() local
113 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2); in mlx5_eswitch_clear_rule_source_port()
114 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, 0); in mlx5_eswitch_clear_rule_source_port()
116 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2); in mlx5_eswitch_clear_rule_source_port()
117 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, 0); in mlx5_eswitch_clear_rule_source_port()
119 if (!memchr_inv(misc2, 0, MLX5_ST_SZ_BYTES(fte_match_set_misc2))) in mlx5_eswitch_clear_rule_source_port()
133 void *misc2; in mlx5_eswitch_set_rule_source_port() local
150 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2); in mlx5_eswitch_set_rule_source_port()
151 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, metadata); in mlx5_eswitch_set_rule_source_port()
153 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2); in mlx5_eswitch_set_rule_source_port()
[all …]
/linux/tools/perf/pmu-events/arch/x86/tigerlake/
H A Dmemory.json192 "EventName": "TX_EXEC.MISC2",
/linux/tools/perf/pmu-events/arch/x86/broadwellde/
H A Dmemory.json299 "EventName": "TX_EXEC.MISC2",
/linux/tools/perf/pmu-events/arch/x86/haswell/
H A Dmemory.json490 "EventName": "TX_EXEC.MISC2",
/linux/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/
H A Ddefiner.c1289 mlx5hws_err(cd->ctx, "Unsupported misc2 parameters set\n"); in hws_definer_conv_misc2()
1320 mlx5hws_err(cd->ctx, "Unsupported misc2 first mpls over gre parameters set\n"); in hws_definer_conv_misc2()
1335 mlx5hws_err(cd->ctx, "Unsupported misc2 first mpls over udp parameters set\n"); in hws_definer_conv_misc2()
/linux/tools/perf/pmu-events/arch/x86/broadwellx/
H A Dmemory.json489 "EventName": "TX_EXEC.MISC2",
/linux/tools/perf/pmu-events/arch/x86/haswellx/
H A Dmemory.json560 "EventName": "TX_EXEC.MISC2",
/linux/tools/perf/pmu-events/arch/x86/rocketlake/
H A Dmemory.json504 "EventName": "TX_EXEC.MISC2",
/linux/tools/perf/pmu-events/arch/x86/icelake/
H A Dmemory.json504 "EventName": "TX_EXEC.MISC2",
/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A Dmemory.json600 "EventName": "TX_EXEC.MISC2",
/linux/tools/perf/pmu-events/arch/x86/skylakex/
H A Dmemory.json1042 "EventName": "TX_EXEC.MISC2",
/linux/tools/perf/pmu-events/arch/x86/skylake/
H A Dmemory.json1202 "EventName": "TX_EXEC.MISC2",
/linux/sound/soc/codecs/
H A D88pm860x-codec.c48 /* Misc2 Register (0x42) */

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