| /linux/Documentation/filesystems/nfs/ |
| H A D | nfsd-io-modes.rst | 115 But NFSD DIRECT does handle misaligned IO in terms of O_DIRECT as best
118 Misaligned READ:
119 If NFSD_IO_DIRECT is used, expand any misaligned READ to the next
124 Misaligned WRITE:
125 If NFSD_IO_DIRECT is used, split any misaligned WRITE into a start,
127 and the start and/or end are misaligned. Buffered IO is used for the
128 misaligned segments and O_DIRECT is used for the middle DIO-aligned
129 segment. DONTCACHE buffered IO is _not_ used for the misaligned
131 performance benefit when handling streaming misaligned WRITEs.
135 misaligned READ to the next DIO-aligned block (on either end of the
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| /linux/Documentation/arch/riscv/ |
| H A D | hwprobe.rst | 297 the performance of misaligned scalar native word accesses on the selected set
301 misaligned scalar accesses is unknown.
303 * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED`: Misaligned scalar
307 * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW`: Misaligned scalar native
309 accesses. Misaligned accesses may be supported directly in hardware, or
312 * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_FAST`: Misaligned scalar native
316 * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED`: Misaligned scalar
317 accesses are not supported at all and will generate a misaligned address
329 performance of misaligned vector accesses on the selected set of processors.
331 * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNKNOWN`: The performance of misaligned
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| H A D | uabi.rst | 67 Misaligned accesses
70 Misaligned scalar accesses are supported in userspace, but they may perform
71 poorly. Misaligned vector accesses are only supported if the Zicclsm extension
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| /linux/arch/hexagon/kernel/ |
| H A D | traps.c | 52 return "Misaligned instruction"; in ex_name()
58 return "Misaligned data load"; in ex_name()
60 return "Misaligned data store"; in ex_name()
232 * It's not clear that misaligned fetches are ever recoverable.
236 die_if_kernel("Misaligned Instruction", regs, 0); in misaligned_instruction()
241 * Misaligned loads and stores, on the other hand, can be
247 die_if_kernel("Misaligned Data Load", regs, 0); in misaligned_data_load()
253 die_if_kernel("Misaligned Data Store", regs, 0); in misaligned_data_store()
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| /linux/tools/testing/selftests/arm64/signal/testcases/ |
| H A D | fake_sigreturn_misaligned_sp.c | 5 * Place a fake sigframe on the stack at a misaligned SP: on sigreturn
25 /* Forcing sigframe on misaligned SP (16 + 3) */ in fake_sigreturn_misaligned_run()
33 .descr = "Triggers a sigreturn with a misaligned sigframe",
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| H A D | testcases.c | 24 *err = "Extra DATAP misaligned"; in validate_extra_context()
26 *err = "Extra SIZE misaligned"; in validate_extra_context()
129 *err = "Misaligned HEAD"; in validate_reserved()
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| /linux/tools/perf/pmu-events/arch/riscv/ |
| H A D | riscv-sbi-firmware.json | 3 "PublicDescription": "Misaligned load trap",
6 "BriefDescription": "Misaligned load trap event"
9 "PublicDescription": "Misaligned store trap",
12 "BriefDescription": "Misaligned store trap event"
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| /linux/drivers/platform/chrome/ |
| H A D | cros_ec_lpc_mec.c | 141 * Long access cannot be used on misaligned data since reading B0 loads in cros_ec_lpc_io_bytes_mec()
156 /* Skip bytes in case of misaligned offset */ in cros_ec_lpc_io_bytes_mec()
168 /* Extra bounds check in case of misaligned length */ in cros_ec_lpc_io_bytes_mec()
174 * Use long auto-increment access except for misaligned write, in cros_ec_lpc_io_bytes_mec()
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| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/ |
| H A D | exception.json | 24 …e the MMU generates a fault, attempting to read or write memory with a misaligned address, interru…
44 …sed by Instruction Aborts. For example, attempting to execute an instruction with a misaligned PC."
48 …e MMU generates a fault,\n2. Attempting to read or write memory with a misaligned address,\n3. Int…
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| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/ |
| H A D | exception.json | 24 …e the MMU generates a fault, attempting to read or write memory with a misaligned address, interru…
44 …sed by Instruction Aborts. For example, attempting to execute an instruction with a misaligned PC."
48 …e MMU generates a fault,\n2. Attempting to read or write memory with a misaligned address,\n3. Int…
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| /linux/arch/riscv/lib/ |
| H A D | csum.c | 111 * Algorithm accounts for buff being misaligned.
202 * misaligned accesses, or when buff is known to be aligned.
259 * Will do a light-weight address alignment if buff is misaligned, unless
260 * cpu supports fast misaligned accesses.
269 * on machines with fast misaligned accesses. in do_csum()
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| H A D | memmove.S | 24 * in the 2 misaligned fixup copy loops.
84 * no need for the full rigmarole of a full misaligned fixup copy.
90 /* Fall through to misaligned fixup copy */
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| /linux/arch/riscv/kernel/ |
| H A D | traps_misaligned.c | 543 * CPUS uses emulated misaligned access at boot time. If that changed in cpu_online_check_unaligned_access_emulated()
547 pr_crit("CPU misaligned accesses non homogeneous (expected all emulated)\n"); in cpu_online_check_unaligned_access_emulated()
557 * We can only support PR_UNALIGN controls if all CPUs have misaligned in check_unaligned_access_emulated_all_cpus()
593 pr_crit("Misaligned trap delegation non homogeneous (expected delegated)"); in cpu_online_sbi_unaligned_setup()
609 pr_info("SBI misaligned access exception delegation ok\n"); in unaligned_access_init()
614 * platform traps on misaligned accesses. in unaligned_access_init()
641 * Either we successfully requested misaligned traps delegation for all in misaligned_traps_can_delegate()
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| H A D | unaligned_access_speed.c | 145 pr_warn("Allocation failure, not measuring misaligned performance\n"); in check_unaligned_access_speed_all_cpus()
156 pr_warn("Allocation failure, not measuring misaligned performance\n"); in check_unaligned_access_speed_all_cpus()
258 pr_warn("Allocation failure, not measuring misaligned performance\n"); in riscv_online_cpu()
299 pr_warn("Allocation failure, not measuring vector misaligned performance\n"); in check_vector_unaligned_access()
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| /linux/drivers/dma/ |
| H A D | pxa_dma.c | 90 bool misaligned; member
113 bool misaligned; member
449 static void phy_enable(struct pxad_phy *phy, bool misaligned) in phy_enable() argument
458 "%s(); phy=%p(%d) misaligned=%d\n", __func__, in phy_enable()
459 phy, phy->idx, misaligned); in phy_enable()
468 if (misaligned) in phy_enable()
511 phy_enable(chan->phy, chan->misaligned); in pxad_launch_chan()
570 to_pxad_sw_desc(vd)->misaligned) in pxad_try_hotchain()
651 chan->misaligned = in pxad_chan_handler()
807 if (chan->misaligned || !to_pxad_sw_desc(vd)->misaligned) in pxad_tx_submit()
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| /linux/tools/testing/selftests/bpf/progs/ |
| H A D | verifier_basic_stack.c | 88 __description("misaligned read from stack")
89 __failure __msg("misaligned stack access")
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| H A D | verifier_xadd.c | 17 __failure __msg("misaligned stack access off")
31 __failure __msg("misaligned value access off")
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| H A D | verifier_int_ptr.c | 67 __description("arg pointer to long misaligned")
68 __failure __msg("misaligned stack access off 0+-20+0 size 8")
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| /linux/Documentation/arch/arm/ |
| H A D | mem_alignment.rst | 5 Too many problems popped up because of unnoticed misaligned memory access in
16 alignment trap can fixup misaligned access for the exception cases, but at
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| /linux/tools/perf/pmu-events/arch/x86/pantherlake/ |
| H A D | memory.json | 181 "BriefDescription": "Counts misaligned loads that are 4K page splits.",
185 …"PublicDescription": "Counts misaligned loads that are 4K page splits. Available PDIST counters: 0…
191 "BriefDescription": "Counts misaligned stores that are 4K page splits.",
195 …"PublicDescription": "Counts misaligned stores that are 4K page splits. Available PDIST counters: …
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| /linux/arch/nios2/kernel/ |
| H A D | misaligned.c | 2 * linux/arch/nios2/kernel/misaligned.c
155 pr_err("fault during kernel misaligned fixup @ %#lx; addr 0x%08x; isn=0x%08x\n", in handle_unaligned_c()
159 pr_err("fault during user misaligned fixup @ %#lx; isn=%08x addr=0x%08x sp=0x%08lx pid=%d\n", in handle_unaligned_c()
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| /linux/tools/perf/pmu-events/arch/x86/grandridge/ |
| H A D | memory.json | 60 "BriefDescription": "Counts misaligned loads that are 4K page splits.",
68 "BriefDescription": "Counts misaligned stores that are 4K page splits.",
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| /linux/arch/arc/kernel/ |
| H A D | traps.c | 75 DO_ERROR_INFO(SIGBUS, "Misaligned Access", do_misaligned_error, BUS_ADRALN)
79 * Entry Point for Misaligned Data access Exception, for emulating in software
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| /linux/arch/arm64/kernel/ |
| H A D | vmlinux.lds.S | 376 "ID map text too big or misaligned")
388 ASSERT(__hyp_bss_start == __bss_start, "HYP and Host BSS are misaligned")
393 ASSERT(_text == KIMAGE_VADDR, "HEAD is misaligned")
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| /linux/arch/sparc/kernel/ |
| H A D | pci_common.c | 146 printk("pci_read_config_word: misaligned reg [%x]\n", in sun4u_read_pci_cfg()
156 printk("pci_read_config_dword: misaligned reg [%x]\n", in sun4u_read_pci_cfg()
235 printk("pci_write_config_word: misaligned reg [%x]\n", in sun4u_write_pci_cfg()
244 printk("pci_write_config_dword: misaligned reg [%x]\n", in sun4u_write_pci_cfg()
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