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/linux/Documentation/devicetree/bindings/net/
H A Dmscc,miim.yaml4 $id: http://devicetree.org/schemas/net/mscc,miim.yaml#
7 title: Microsemi MII Management Controller (MIIM)
18 - mscc,ocelot-miim
19 - microchip,lan966x-miim
62 compatible = "mscc,ocelot-miim";
/linux/Documentation/devicetree/bindings/mfd/
H A Dmscc,ocelot.yaml54 $ref: /schemas/net/mscc,miim.yaml
58 - mscc,ocelot-miim
97 compatible = "mscc,ocelot-miim";
108 compatible = "mscc,ocelot-miim";
134 function = "miim";
/linux/arch/arm64/boot/dts/microchip/
H A Dsparx5.dtsi286 function = "miim";
291 function = "miim";
296 function = "miim";
426 compatible = "mscc,ocelot-miim";
434 compatible = "mscc,ocelot-miim";
444 compatible = "mscc,ocelot-miim";
454 compatible = "mscc,ocelot-miim";
/linux/drivers/pinctrl/
H A Dpinctrl-ocelot.c258 [FUNC_MIIM] = "miim",
560 OCELOT_P(14, MIIM, TWI_SCL_M, SFP);
561 OCELOT_P(15, MIIM, TWI_SCL_M, SFP);
664 JAGUAR2_P(56, MIIM, SFP);
665 JAGUAR2_P(57, MIIM, SFP);
666 JAGUAR2_P(58, MIIM, SFP);
667 JAGUAR2_P(59, MIIM, SFP);
776 SERVALT_P(22, MIIM, SFP, TWI2);
777 SERVALT_P(23, MIIM, SFP, TWI2);
898 SPARX5_P(52, SFP, MIIM, TWI_SCL_M);
[all …]
/linux/arch/mips/boot/dts/mscc/
H A Docelot.dtsi231 function = "miim";
239 compatible = "mscc,ocelot-miim";
261 compatible = "mscc,ocelot-miim";
/linux/drivers/net/dsa/microchip/
H A Dksz8.c799 * ksz8_r_phy_ctrl - Translates and reads from the SMI interface to a MIIM PHY
806 * bit values into their corresponding control settings for a MIIM PHY Control
843 * ksz8_r_phy_bmcr - Translates and reads from the SMI interface to a MIIM PHY
850 * bit values into their corresponding control settings for a MIIM PHY Basic
853 * MIIM Bit Mapping Comparison between KSZ8794 and KSZ8873
855 * MIIM Bit | KSZ8794 Reg/Bit | KSZ8873 Reg/Bit
1058 * ksz8_w_phy_ctrl - Translates and writes to the SMI interface from a MIIM PHY
1064 * This function translates control settings from a MIIM PHY Control register
1090 * ksz8_w_phy_bmcr - Translates and writes to the SMI interface from a MIIM PHY
1096 * This function translates control settings from a MIIM PHY Basic mode control
[all …]
/linux/drivers/mfd/
H A Docelot-core.c175 .of_compatible = "mscc,ocelot-miim",
182 .of_compatible = "mscc,ocelot-miim",
/linux/drivers/net/mdio/
H A DKconfig144 tristate "Microsemi MIIM interface support"
148 This driver supports the MIIM (MDIO) interface found in the network
H A DMakefile19 obj-$(CONFIG_MDIO_MSCC_MIIM) += mdio-mscc-miim.o
/linux/drivers/net/ethernet/oki-semi/pch_gbe/
H A Dpch_gbe.h63 u32 MIIM; member
104 #define PCH_GBE_INT_MIIM_CMPLT 0x00010000 /* MIIM I/F Read completion */
238 /* MIIM */
H A Dpch_gbe_main.c464 * pch_gbe_mac_ctrl_miim - Control MIIM interface
482 if (readx_poll_timeout_atomic(ioread32, &hw->reg->MIIM, data_out, in pch_gbe_mac_ctrl_miim()
484 netdev_err(adapter->netdev, "pch-gbe.miim won't go Ready\n"); in pch_gbe_mac_ctrl_miim()
490 dir | data), &hw->reg->MIIM); in pch_gbe_mac_ctrl_miim()
491 readx_poll_timeout_atomic(ioread32, &hw->reg->MIIM, data_out, in pch_gbe_mac_ctrl_miim()
/linux/drivers/net/ethernet/xilinx/
H A Dll_temac_mdio.c30 /* Write the PHY address to the MIIM Access Initiator register. in temac_mdio_read()
H A Dxilinx_axienet.h318 #define XAE_MDIO_INT_MIIM_RDY_MASK 0x00000001 /* MIIM Interrupt */
/linux/drivers/net/ethernet/freescale/
H A Dxgmac_mdio.c204 * TSEC1 MIIM regs.
263 * TSEC1 MIIM regs.
/linux/arch/arm/boot/dts/microchip/
H A Dlan966x-kontron-kswitch-d10-mmt.dtsi61 miim_c_pins: miim-c-pins {
H A Dlan966x.dtsi530 compatible = "microchip,lan966x-miim";
539 compatible = "microchip,lan966x-miim";
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588-extra-pinctrl.dtsi62 gmac0_miim: gmac0-miim {
H A Drk3568-pinctrl.dtsi569 gmac0_miim: gmac0-miim {
638 gmac1m0_miim: gmac1m0-miim {
705 gmac1m1_miim: gmac1m1-miim {
H A Drk3588-base-pinctrl.dtsi437 gmac1_miim: gmac1-miim {
/linux/arch/arm/boot/dts/rockchip/
H A Drv1126-pinctrl.dtsi374 rgmiim1_miim: rgmiim1-miim {