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/linux/drivers/net/phy/aquantia/
H A Daquantia_main.c1 // SPDX-License-Identifier: GPL-2.0
104 /* Sleep and timeout for checking if the Processor-Intensive
127 int len_l = min(stat->size, 16); in aqr107_get_stat()
128 int len_h = stat->size - len_l; in aqr107_get_stat()
132 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg); in aqr107_get_stat()
136 ret = val & GENMASK(len_l - 1, 0); in aqr107_get_stat()
138 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1); in aqr107_get_stat()
142 ret += (val & GENMASK(len_h - 1, 0)) << 16; in aqr107_get_stat()
151 struct aqr107_priv *priv = phydev->priv; in aqr107_get_stats()
161 priv->sgmii_stats[i] += val; in aqr107_get_stats()
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/linux/drivers/net/phy/
H A Dmarvell.c1 // SPDX-License-Identifier: GPL-2.0+
189 /* RGMII to 1000BASE-X */
191 /* RGMII to 100BASE-FX */
391 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in marvell_config_intr()
455 err = marvell_set_polarity(phydev, phydev->mdix_ctrl); in marvell_config_aneg()
470 if (phydev->autoneg != AUTONEG_ENABLE || changed) { in marvell_config_aneg()
488 * that certain registers get written in order in m88e1101_config_aneg()
520 * marvell,reg-init property stored in the of_node for the phydev.
522 * marvell,reg-init = <reg-page reg mask value>,...;
524 * There may be one or more sets of <reg-page reg mask value>:
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/linux/drivers/net/ethernet/chelsio/cxgb4/
H A Dt4_hw.c4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
43 * t4_wait_op_done_val - wait until an operation is completed
46 * @mask: a single-bit field within @reg that indicates completion
55 * operation completes and -EAGAIN otherwise.
68 if (--attempts == 0) in t4_wait_op_done_val()
69 return -EAGAIN; in t4_wait_op_done_val()
83 * t4_set_reg_field - set a register field to a value
102 * t4_read_indirect - read indirectly addressed registers
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