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Searched full:macrotile (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/imagination/
H A Dpvr_rogue_cr_defs_client.h59 /* MacroTile Boundaries X Plane */
64 * X1 MacroTile boundary, left tile X for second column of macrotiles (16MT mode) - 32 pixels across
70 * X2 MacroTile boundary, left tile X for third(16MT) column of macrotiles - 32 pixels across tile
75 * X3 MacroTile boundary, left tile X for fourth column of macrotiles (16MT) - 32 pixels across tile
80 /* MacroTile Boundaries Y Plane. */
85 * X1 MacroTile boundary, ltop tile Y for second column of macrotiles (16MT mode) - 32 pixels tile
91 * X2 MacroTile boundary, top tile Y for third(16MT) column of macrotiles - 32 pixels tile height
96 * X3 MacroTile boundary, top tile Y for fourth column of macrotiles (16MT) - 32 pixels tile height
143 * Macrotile width, in tiles. A value of zero corresponds to the maximum size
150 * Macrotile height, in tiles. A value of zero corresponds to the maximum size
H A Dpvr_hwrt.c22 * struct pvr_rt_mtile_info - Render target macrotile information
260 * Set up 16 macrotiles with a multiple of 2x2 tiles per macrotile, which is in hwrt_init_common_fw_structure()
272 /* Set up 16 macrotiles with a multiple of 4x4 tiles per macrotile. */ in hwrt_init_common_fw_structure()
/linux/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_8_1_sm8450.h369 /* TODO: macrotile-qseed is different from macrotile */
H A Ddpu_9_1_sar2130p.h364 /* TODO: macrotile-qseed is different from macrotile */
H A Ddpu_9_0_sm8550.h364 /* TODO: macrotile-qseed is different from macrotile */
H A Ddpu_8_0_sc8280xp.h387 /* TODO: macrotile-qseed is different from macrotile */
H A Ddpu_8_4_sa8775p.h408 /* TODO: macrotile-qseed is different from macrotile */
H A Ddpu_9_2_x1e80100.h404 /* TODO: macrotile-qseed is different from macrotile */
H A Ddpu_13_0_kaanapali.h446 /* TODO: macrotile-qseed is different from macrotile */
/linux/include/uapi/drm/
H A Ddrm_fourcc.h826 * Each macrotile consists of m x n (mostly 4 x 4) tiles.
827 * Pixel data pitch/stride is aligned with macrotile width.
828 * Pixel data height is aligned with macrotile height.
839 * Each macrotile consists of m x n (mostly 4 x 4) tiles.
840 * Pixel data pitch/stride is aligned with macrotile width.
841 * Pixel data height is aligned with macrotile height.
H A Dradeon_drm.h1027 /* CIK macrotile mode array */
H A Dpvr_drm.h930 /** @macrotile_array_dev_addr: [IN] Macrotile array GPU virtual address. */
/linux/drivers/gpu/drm/radeon/
H A Dradeon_kms.c507 DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n"); in radeon_info_ioctl()