Searched +full:ls1028a +full:- +full:enetc +full:- +full:ierb (Results 1 – 3 of 3) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/net/fsl,enetc-ierb.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#11 which preconfigures the FIFO limits for the ENETC ports.14 - Frank Li <Frank.Li@nxp.com>15 - Vladimir Oltean <vladimir.oltean@nxp.com>16 - Wei Fang <wei.fang@nxp.com>17 - Claudiu Manoil <claudiu.manoil@nxp.com>22 - fsl,ls1028a-enetc-ierb[all …]
1 * ENETC ethernet device tree bindings3 Depending on board design and ENETC port type (internal or9 - reg : Specifies PCIe Device Number and Function10 Number of the ENETC endpoint device, according12 - compatible : Should be "fsl,enetc".14 1. The ENETC external port is connected to a MDIO configurable phy16 1.1. Using the local ENETC Port MDIO interface18 In this case, the ENETC node should include a "mdio" sub-node19 that in turn should contain the "ethernet-phy" node describing the26 - phy-handle : Phandle to a PHY on the MDIO bus.[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)3 * Device Tree Include file for NXP Layerscape-1028A family SoC.5 * Copyright 2018-2020 NXP11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>12 #include <dt-bindings/interrupt-controller/arm-gic.h>13 #include <dt-bindings/thermal/thermal.h>16 compatible = "fsl,ls1028a";17 interrupt-parent = <&gic>;18 #address-cells = <2>;19 #size-cells = <2>;[all …]