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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dmstar,mst-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/mstar,mst-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark-PK Tsai <mark-pk.tsai@mediatek.com>
21 const: mstar,mst-intc
23 interrupt-controller: true
25 "#interrupt-cells":
33 mstar,irqs-map-range:
35 The range <start, end> of parent interrupt controller's interrupt
[all …]
/linux/drivers/net/ethernet/intel/ice/
H A Dice_irq.c1 // SPDX-License-Identifier: GPL-2.0
9 * ice_init_irq_tracker - initialize interrupt tracker
18 pf->irq_tracker.num_entries = max_vectors; in ice_init_irq_tracker()
19 pf->irq_tracker.num_static = num_static; in ice_init_irq_tracker()
20 xa_init_flags(&pf->irq_tracker.entries, XA_FLAGS_ALLOC); in ice_init_irq_tracker()
26 pf->virt_irq_tracker.bm = bitmap_zalloc(num_entries, GFP_KERNEL); in ice_init_virt_irq_tracker()
27 if (!pf->virt_irq_tracker.bm) in ice_init_virt_irq_tracker()
28 return -ENOMEM; in ice_init_virt_irq_tracker()
30 pf->virt_irq_tracker.num_entries = num_entries; in ice_init_virt_irq_tracker()
31 pf->virt_irq_tracker.base = base; in ice_init_virt_irq_tracker()
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/linux/drivers/soc/ti/
H A Dknav_qmss_queue.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
12 #include <linux/dma-mapping.h>
44 * are to be re-defined
57 (kdev->instances + (idx << kdev->inst_shift))
60 list_for_each_entry_rcu(qh, &inst->handles, list, \
64 for (idx = 0, inst = kdev->instances; \
65 idx < (kdev)->num_queues_in_use; \
84 * @inst: - qmss queue instance like accumulator
95 if (atomic_read(&qh->notifier_enabled) <= 0) in knav_queue_notify()
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/linux/drivers/irqchip/
H A Dirq-econet-en751221.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * be routed to either VPE but not both, so to support per-CPU interrupts, a
13 * If an interrupt (say 30) needs per-CPU capability, the SoC integrator
15 * reflects this by adding the pair <30 29> to the "econet,shadow-interrupts"
46 * - NOT_PERCPU: This interrupt is not per-cpu, so it has no shadow
47 * - IS_SHADOW: This interrupt is a shadow of another per-cpu interrupt
48 * - else: This is a per-cpu interrupt whose shadow is the value
57 /* IRQs must be disabled */
70 /* IRQs must be disabled */
78 * It should only be masked/unmasked as a result of the "real" per-cpu in econet_chmask()
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H A Dirq-ti-sci-inta.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/
24 #include <asm-generic/msi.h>
44 * struct ti_sci_inta_event_desc - Description of an event coming to
59 * struct ti_sci_inta_vint_desc - Description of a virtual interrupt coming out
78 * struct ti_sci_inta_irq_domain - Structure representing a TISCI based
87 * @ti_sci_id: TI-SCI device identifier
89 * @unmapped_dev_ids: Pointer to an array of TI-SCI device identifiers of
91 * Unmapped Events are not part of the Global Event Map and
95 * generating Unmapped Event, we must use the INTA's TI-SCI
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H A Dirq-mst-intc.c1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
4 * Author Mark-PK Tsai <mark-pk.tsai@mediatek.com>
49 raw_spin_lock_irqsave(&cd->lock, flags); in mst_set_irq()
50 val = readw_relaxed(cd->base + offset) | mask; in mst_set_irq()
51 writew_relaxed(val, cd->base + offset); in mst_set_irq()
52 raw_spin_unlock_irqrestore(&cd->lock, flags); in mst_set_irq()
65 raw_spin_lock_irqsave(&cd->lock, flags); in mst_clear_irq()
66 val = readw_relaxed(cd->base + offset) & ~mask; in mst_clear_irq()
67 writew_relaxed(val, cd->base + offset); in mst_clear_irq()
68 raw_spin_unlock_irqrestore(&cd->lock, flags); in mst_clear_irq()
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H A Dirq-i8259.c6 * Code to handle x86 style IRQs plus some generic interrupt stuff.
9 * Copyright (C) 1994 - 2000 Ralf Baechle
35 static int i8259A_auto_eoi = -1;
44 .name = "XT-PIC",
70 unsigned int mask, irq = d->irq - I8259A_IRQ_BASE; in disable_8259A_irq()
85 unsigned int mask, irq = d->irq - I8259A_IRQ_BASE; in enable_8259A_irq()
136 unsigned int irqmask, irq = d->irq - I8259A_IRQ_BASE; in mask_and_ack_8259A()
143 * to overdo spurious IRQ handling - it's usually a sign in mask_and_ack_8259A()
147 * Note that IRQ7 and IRQ15 (the two spurious IRQs in mask_and_ack_8259A()
148 * usually resulting from the 8259A-1|2 PICs) occur in mask_and_ack_8259A()
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/linux/arch/arm/boot/dts/sigmastar/
H A Dmstar-v7.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/mstar-msc313-mpll.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
14 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a7";
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/linux/drivers/pci/msi/
H A Dapi.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCI MSI/MSI-X — Exported APIs for device drivers
5 * Copyright (C) 2003-2004 Intel
17 * pci_enable_msi() - Enable MSI interrupt mode on device
22 * Linux IRQ will be saved at @dev->irq. The driver must invoke
40 * pci_disable_msi() - Disable MSI interrupt mode on device
45 * The PCI device Linux IRQ (@dev->irq) is restored to its default
46 * pin-assertion IRQ. This is the cleanup pair of pci_enable_msi().
53 if (!pci_msi_enabled() || !dev || !dev->msi_enabled) in pci_disable_msi()
56 guard(msi_descs_lock)(&dev->dev); in pci_disable_msi()
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/linux/arch/powerpc/platforms/52xx/
H A Dmpc52xx_pic.c23 * -----------------
26 * group has 3 irqs, External IRQ0, slice timer 0 irq, and wake from deep
27 * sleep. Main group include the other 3 external IRQs, slice timer 1, RTC,
29 * remaining irq sources from all of the on-chip peripherals (PSCs, Ethernet,
33 * -----
39 * a unique range of the global IRQ# space.
41 * To define a range of virq numbers for this controller, this driver first
61 * -------------------
62 * For actually manipulating IRQs (masking, enabling, clearing, etc) this
74 * register even though one of the external IRQs is in the critical group and
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/linux/drivers/pci/hotplug/
H A Dcpqphp_ctrl.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
72 func = cpqhp_slot_find(ctrl->bus, in handle_switch_change()
73 (hp_slot + ctrl->slot_device_offset), 0); in handle_switch_change()
78 taskInfo = &(ctrl->event_queue[ctrl->next_event]); in handle_switch_change()
79 ctrl->next_event = (ctrl->next_event + 1) % 10; in handle_switch_change()
80 taskInfo->hp_slot = hp_slot; in handle_switch_change()
84 temp_word = ctrl->ctrl_int_comp >> 16; in handle_switch_change()
85 func->presence_save = (temp_word >> hp_slot) & 0x01; in handle_switch_change()
86 func->presence_save |= (temp_word >> (hp_slot + 7)) & 0x02; in handle_switch_change()
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/linux/arch/powerpc/platforms/embedded6xx/
H A Dflipper-pic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * arch/powerpc/platforms/embedded6xx/flipper-pic.c
6 * Copyright (C) 2004-2009 The GameCube Linux Team
9 #define DRV_MODULE_NAME "flipper-pic"
20 #include "flipper-pic.h"
84 .name = "flipper-pic",
101 irq_set_chip_data(virq, h->host_data); in flipper_pic_map()
108 .map = flipper_pic_map,
118 /* mask and ack all IRQs */ in __flipper_quiesce()
136 if (!of_device_is_compatible(pi, "nintendo,flipper-pi")) { in flipper_pic_init()
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H A Dhlwd-pic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * arch/powerpc/platforms/embedded6xx/hlwd-pic.c
9 #define DRV_MODULE_NAME "hlwd-pic"
19 #include "hlwd-pic.h"
81 .name = "hlwd-pic",
98 irq_set_chip_data(virq, h->host_data); in hlwd_pic_map()
105 .map = hlwd_pic_map,
110 void __iomem *io_base = h->host_data; in __hlwd_pic_get_irq()
116 return 0; /* no more IRQs pending */ in __hlwd_pic_get_irq()
127 raw_spin_lock(&desc->lock); in hlwd_pic_irq_cascade()
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/linux/drivers/mfd/
H A Dmax14577.c1 // SPDX-License-Identifier: GPL-2.0+
3 // max14577.c - mfd core driver for the Maxim 14577/77836
18 #include <linux/mfd/max14577-private.h>
42 * maxim_charger_calc_reg_current - Calculate register value for current
54 * - is always between <limits.min, limits.max>;
55 * - is always less or equal to max_ua;
56 * - is the highest possible value;
57 * - may be lower than min_ua.
59 * On success returns 0. On error returns -EINVAL (requested min/max current
68 return -EINVAL; in maxim_charger_calc_reg_current()
[all …]
/linux/arch/powerpc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
5 def_bool PPC64 && $(cc-option, -mabi=elfv2)
8 def_bool PPC64 && $(cc-option, -mcpu=power10 -mprefixed)
11 # Clang has a bug (https://github.com/llvm/llvm-project/issues/62372)
12 # where pcrel code is not generated if -msoft-float, -mno-altivec, or
13 # -mno-vsx options are also given. Without these options, fp/vec
16 def_bool PPC64 && CC_IS_GCC && $(cc-option, -mcpu=power10 -mpcrel)
35 # On Book3S 64, the default virtual address space for 64-bit processes
38 # between bottom-up and top-down allocations for applications that
41 default 29 if PPC_BOOK3S_64 && PPC_64K_PAGES # 29 = 45 (32T) - 16 (64K)
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/linux/arch/powerpc/platforms/44x/
H A Dhsta_msi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
18 #include <asm/ppc-pci.h>
30 /* An array mapping offsets to hardware IRQs */
45 /* We don't support MSI-X */ in hsta_setup_msi_irqs()
47 pr_debug("%s: MSI-X not supported.\n", __func__); in hsta_setup_msi_irqs()
48 return -EINVAL; in hsta_setup_msi_irqs()
51 msi_for_each_desc(entry, &dev->dev, MSI_DESC_NOTASSOCIATED) { in hsta_setup_msi_irqs()
62 return -EINVAL; in hsta_setup_msi_irqs()
66 * HSTA generates interrupts on writes to 128-bit aligned in hsta_setup_msi_irqs()
84 return -EINVAL; in hsta_setup_msi_irqs()
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/linux/drivers/pinctrl/nomadik/
H A Dpinctrl-abx500.h1 /* SPDX-License-Identifier: GPL-2.0 */
34 * struct abx500_function - ABx500 pinctrl mux function
46 * struct abx500_pingroup - describes a ABx500 pin group
49 * from the driver-local pin enumeration space
73 #define UNUSED -1
109 * struct abx500_gpio_irq_cluster - indicates GPIOs which are interrupt
113 * @to_irq: The ABx500 GPIO's associated IRQs are clustered
116 * read-in values into the cluster information table
126 * struct abx500_pinrange - map pin numbers to GPIO offsets
129 * @npins: number of pins to map from both offsets
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/linux/include/linux/
H A Dregmap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * Register map access API
54 #define REGMAP_UPSHIFT(s) (-(s))
73 * struct reg_default - Default value for a register.
87 * struct reg_sequence - An individual write from a sequence of writes.
110 * regmap_read_poll_timeout - Poll until a condition is met or a timeout occurs
112 * @map: Regmap to read from
116 * @sleep_us: Maximum time to sleep between reads in us (0 tight-loops). Please
123 * Returns: 0 on success and -ETIMEDOUT upon a timeout or the regmap_read
128 #define regmap_read_poll_timeout(map, addr, val, cond, sleep_us, timeout_us) \ argument
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/linux/arch/arm/mm/
H A Dcache-uniphier.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2015-2016 Socionext Inc.
15 #include <asm/hardware/cache-uniphier.h>
21 #define UNIPHIER_SSCC_ACT BIT(19) /* Inst-Data separate */
23 #define UNIPHIER_SSCC_PRD BIT(17) /* enable pre-fetch */
37 #define UNIPHIER_SSCOPE_CM_FLUSH_PREFETCH 0x9 /* flush p-fetch buf */
56 /* Is the operation region specified by address range? */
61 * struct uniphier_cache_data - UniPhier outer cache specific data
71 * @range_op_max_size: max size that can be handled by a single range operation
93 * __uniphier_cache_sync - perform a sync point for a particular cache level
[all …]
/linux/arch/sparc/kernel/
H A Dleon_pci_grpci1.c1 // SPDX-License-Identifier: GPL-2.0
36 * GRPCI1 APB Register MAP
44 unsigned int iomap; /* 0x14 IO Map */
85 struct grpci1_regs __iomem *regs; /* GRPCI register map */
89 unsigned char irq_map[4]; /* GRPCI nexus PCI INTX# IRQs */
108 struct grpci1_priv *priv = dev->bus->sysdata; in grpci1_map_irq()
113 pin = ((pin - 1) + irq_group) & 0x3; in grpci1_map_irq()
115 return priv->irq_map[pin]; in grpci1_map_irq()
124 return -EINVAL; in grpci1_cfg_r32()
134 cfg = REGLOAD(priv->regs->cfg_stat); in grpci1_cfg_r32()
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/linux/Documentation/networking/device_drivers/ethernet/stmicro/
H A Dstmmac.rst1 .. SPDX-License-Identifier: GPL-2.0+
13 - In This Release
14 - Feature List
15 - Kernel Configuration
16 - Command Line Parameters
17 - Driver Information and Notes
18 - Debug Information
19 - Support
33 (and older) and DesignWare(R) Cores Ethernet Quality-of-Service version 4.0
35 DesignWare(R) Cores XGMAC - 10G Ethernet MAC and DesignWare(R) Cores
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/linux/drivers/pci/controller/
H A Dvmd.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/irqchip/irq-msi-lib.h>
15 #include <linux/pci-acpi.h>
16 #include <linux/pci-ecam.h>
56 * vendor-specific capability space
61 * Device may use MSI-X vector 0 for software triggering and will not
67 * Device can bypass remapping MSI-X transactions into its MSI-X table,
97 * struct vmd_irq - private data to map driver IRQ to the VMD shared vector
103 * Every MSI/MSI-X IRQ requested for a device in a VMD domain will be mapped to
114 * struct vmd_irq_list - list of driver requested IRQs mapping to a VMD vector
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/linux/Documentation/PCI/
H A Dpci.rst1 .. SPDX-License-Identifier: GPL-2.0
7 :Authors: - Martin Mares <mj@ucw.cz>
8 - Grant Grundler <grundler@parisc-linux.org>
11 Since each CPU architecture implements different chip-sets and PCI devices
18 by Jonathan Corbet, Alessandro Rubini, and Greg Kroah-Hartman.
26 "Linux PCI" <linux-pci@atrey.karlin.mff.cuni.cz> mailing list.
38 supporting hot-pluggable PCI, CardBus, and Express-Card in a single driver].
45 - Enable the device
46 - Request MMIO/IOP resources
47 - Set the DMA mask size (for both coherent and streaming DMA)
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/linux/drivers/pinctrl/qcom/
H A Dpinctrl-msm.c1 // SPDX-License-Identifier: GPL-2.0-only
25 #include <linux/pinctrl/pinconf-generic.h>
33 #include "../pinctrl-utils.h"
36 #include "pinctrl-msm.h"
43 * struct msm_pinctrl - state for a pinctrl-msm device
52 * @enabled_irqs: Bitmap of currently enabled irqs.
53 * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
55 * @skip_wake_irqs: Skip IRQs that are handled by wakeup interrupt controller
56 * @disabled_for_mux: These IRQs were disabled because we muxed away.
89 return readl(pctrl->regs[g->tile] + g->name##_reg); \
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/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7d.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
7 #include <dt-bindings/reset/imx7-reset.h>
18 clock-frequency = <996000000>;
19 operating-points-v2 = <&cpu0_opp_table>;
20 #cooling-cells = <2>;
21 nvmem-cells = <&fuse_grade>;
22 nvmem-cell-names = "speed_grade";
26 compatible = "arm,cortex-a7";
29 clock-frequency = <996000000>;
30 operating-points-v2 = <&cpu0_opp_table>;
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