Searched +full:ipq806x +full:- +full:nand (Results 1 – 3 of 3) sorted by relevance
1 // SPDX-License-Identifier: GPL-2.02 /dts-v1/;4 #include <dt-bindings/interrupt-controller/arm-gic.h>5 #include <dt-bindings/mfd/qcom-rpm.h>6 #include <dt-bindings/clock/qcom,rpmcc.h>7 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>8 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>9 #include <dt-bindings/gpio/gpio.h>10 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>11 #include <dt-bindings/soc/qcom,gsbi.h>[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Christian Marangi <ansuelsmth@gmail.com>11 - Bjorn Andersson <bjorn.andersson@linaro.org>15 peripheral buses such as NAND and SPI.27 "#dma-cells":32 - description: phandle to the core clock33 - description: phandle to the iface clock35 clock-names:[all …]
1 // SPDX-License-Identifier: GPL-2.0-only9 #include <linux/dma-mapping.h>18 #include <linux/mtd/nand-qpic-common.h>21 * NAND special boot partitions57 * NAND chip structure62 * @chip: base NAND chip structure82 * ecc/non-ecc mode for the current nand flash132 ((u8 *)chip->controller - sizeof(struct qcom_nand_controller)); in get_qcom_nand_controller()137 return ioread32(nandc->base + offset); in nandc_read()143 iowrite32(val, nandc->base + offset); in nandc_write()[all …]