| /linux/drivers/gpu/drm/i915/gt/ |
| H A D | intel_gt_types.h | 110 /* Serialize global tlb invalidations */
114 * Batch TLB invalidations
119 * so we track how many TLB invalidations have been
|
| /linux/Documentation/arch/x86/ |
| H A D | tlb.rst | 41 You may be doing too many individual invalidations if you see the
43 profiles. If you believe that individual invalidations being
|
| H A D | sva.rst | 78 - Register for mmu_notifier() to track any page-table invalidations to keep
|
| /linux/arch/powerpc/include/asm/ |
| H A D | mmu_context.h | 135 * in order to force TLB invalidations to be global as to in mm_context_add_copro()
159 * for the time being. Invalidations will remain global if in mm_context_remove_copro()
161 * it could make some invalidations local with no flush in mm_context_remove_copro()
|
| H A D | mmu.h | 76 /* Enable use of broadcast TLB invalidations. We don't always set it
78 * use of such invalidations
|
| /linux/arch/sh/mm/ |
| H A D | cache-shx3.c | 39 * Broadcast I-cache block invalidations by default. in shx3_cache_init()
|
| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/ |
| H A D | l2_cache.json | 12 …h return data even if the snoops cause an invalidation. L2 cache line invalidations which do not w…
|
| H A D | l1d_cache.json | 12 …nce operations. The following cache operations are not counted:\n\n1. Invalidations which do not r…
|
| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/ |
| H A D | l2_cache.json | 12 …h return data even if the snoops cause an invalidation. L2 cache line invalidations which do not w…
|
| H A D | l1d_cache.json | 12 …nce operations. The following cache operations are not counted:\n\n1. Invalidations which do not r…
|
| /linux/arch/openrisc/include/asm/ |
| H A D | cacheflush.h | 32 * invalidations need to be broadcasted to all other cpu in the system in
|
| /linux/drivers/infiniband/hw/mlx5/ |
| H A D | odp.c | 280 u64 invalidations = 0; in mlx5_ib_invalidate_range() local
307 * overwrite the same MTTs. Concurent invalidations might race us, in mlx5_ib_invalidate_range()
332 /* Count page invalidations */ in mlx5_ib_invalidate_range()
333 invalidations += idx - blk_start_idx + 1; in mlx5_ib_invalidate_range()
342 /* Count page invalidations */ in mlx5_ib_invalidate_range()
343 invalidations += idx - blk_start_idx + 1; in mlx5_ib_invalidate_range()
346 mlx5_update_odp_stats_with_handled(mr, invalidations, invalidations); in mlx5_ib_invalidate_range()
|
| /linux/include/uapi/rdma/ |
| H A D | rdma_user_ioctl.h | 80 /* read TID cache invalidations */
|
| /linux/drivers/iommu/intel/ |
| H A D | pasid.c | 317 * - Flush the caches per Table 28 ”Guidance to Software for Invalidations“
624 * From VT-d spec table 25 "Guidance to Software for Invalidations": in intel_pasid_setup_dirty_tracking()
1123 * Cache invalidations after change in a context table entry that was present
1124 * according to the Spec 6.5.3.3 (Guidance to Software for Invalidations).
|
| /linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/ |
| H A D | cache.json | 39 … which return data, regardless of whether they cause an invalidation. Invalidations from the L2 wh…
|
| /linux/Documentation/devicetree/bindings/arm/ |
| H A D | arm,cci-400.yaml | 15 and manage coherency, TLB invalidations and memory barriers.
|
| /linux/tools/perf/pmu-events/arch/arm64/arm/cmn/sys/ |
| H A D | cmn.json | 54 "BriefDescription": "Counts number of SF eviction cache invalidations initiated.",
|
| /linux/fs/xfs/scrub/ |
| H A D | reap.c | 170 * of buffer invalidations to 2048.
441 * buffer invalidations, so we need to return early so that we can in xreap_agextent_iter()
1199 * transaction is full of logged buffer invalidations, so we need to in xrep_reap_bmapi_iter()
|
| /linux/arch/arm64/kvm/hyp/ |
| H A D | pgtable.c | 826 * TLB invalidations until the entire walk is finished, and in stage2_unmap_defer_tlb_flush()
828 * invalidations. Condition deferred TLB invalidation on the in stage2_unmap_defer_tlb_flush()
1143 /* Perform the deferred TLB invalidations */ in kvm_pgtable_stage2_unmap()
|
| /linux/arch/arm/mm/ |
| H A D | proc-v6.S | 227 @ complete invalidations
|
| /linux/arch/powerpc/mm/nohash/ |
| H A D | tlb_low.S | 4 * types of TLB invalidations on various processors with no hash
|
| /linux/arch/hexagon/include/asm/ |
| H A D | pgtable.h | 140 * For now, assume that higher-level code will do TLB/MMU invalidations
|
| /linux/drivers/infiniband/hw/hfi1/ |
| H A D | user_exp_rcv.c | 926 * driver to process TID cache invalidations is in tid_rb_invalidate()
927 * expensive and TID cache invalidations are in tid_rb_invalidate()
|
| /linux/drivers/iommu/riscv/ |
| H A D | iommu.c | 828 * Protection domain requiring IOATC and DevATC translation cache invalidations,
917 * This limit will be replaced with range invalidations, if supported by
919 * range invalidations update will be available.
|
| /linux/drivers/gpu/drm/xe/ |
| H A D | xe_svm.c | 143 * invalidations spanning multiple ranges. in xe_svm_range_notifier_event_begin()
210 * out if an invalidations is need, but also not ideal. in xe_svm_invalidate()
|