| /titanic_52/usr/src/uts/common/io/atge/ |
| H A D | atge_l1.c | 804 * Disable interrupts. in atge_l1_interrupt()
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| /titanic_52/usr/src/cmd/mdb/sparc/kmdb/ |
| H A D | kaif.c | 594 * we need keep interrupts disabled. If it's a branch, we may need in kaif_step()
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| /titanic_52/usr/src/uts/sun4/os/ |
| H A D | machdep.c | 753 * mstate while handling interrupts. Such time should be reported
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| /titanic_52/usr/src/uts/common/io/ |
| H A D | mem.c | 860 * to go into an infinite loop at pil 13 and no interrupts in mmsegmap()
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| /titanic_52/usr/src/uts/common/io/xge/hal/xgehal/ |
| H A D | xgehal-stats.c | 853 * number of completions per interrupt, number of traffic interrupts, etc.
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| /titanic_52/usr/src/uts/common/io/scsi/adapters/pmcs/ |
| H A D | pmcs_nvram.c | 42 * interrupts are enabled.
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| /titanic_52/usr/src/cmd/bc/ |
| H A D | bc.y | 849 (void) signal(SIGINT, SIG_IGN); /* ignore all interrupts */ in yyinit()
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| /titanic_52/usr/src/uts/common/io/nxge/ |
| H A D | nxge_hio_guest.c | 545 * Uninitialize interrupts. in nxge_hio_vr_release()
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| /titanic_52/usr/src/cmd/auditd/ |
| H A D | auditd.c | 32 * The major interrupts are SIGHUP (start over), SIGTERM (start shutting down),
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| /titanic_52/usr/src/uts/common/io/mwl/ |
| H A D | mwl.c | 2461 mwl_hal_intrset(sc, 0); /* disable interrupts */ in mwl_chan_set()
3455 * Enable interrupts. in mwl_init()
4092 "no fixed interrupts\n"); in mwl_attach()
4325 * Disable all interrupts in mwl_quiesce()
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| /titanic_52/usr/src/uts/sun4u/starfire/io/ |
| H A D | drmach.c | 2394 * cpu's ecache, disabling interrupts (by turning of the ET bit in in drmach_cpu_obp_detach()
3736 * Quiesce interrupts on the target CPU. We do this by setting in drmach_cpu_poweroff()
3739 * This prevents the processor from receiving any new soft interrupts. in drmach_cpu_poweroff()
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| /titanic_52/usr/src/uts/common/sys/ |
| H A D | dtrace_impl.h | 309 * call context, interrupts are disabled, and the active and the inactive
312 * inactive equivalents, and clearing the state fields. Because interrupts are
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| H A D | kstat.h | 562 * Measurement of the spurious class of interrupts is useful for
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| /titanic_52/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/ |
| H A D | lm_hw_attn.c | 155 //mask read length error interrupts in brb for parser (parsing unit and 'checksum and crc' unit) in enable_blocks_attention()
1843 /* Disable HW interrupts */ in lm_handle_deassertion_processing()
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| /titanic_52/usr/src/uts/common/io/ib/adapters/tavor/ |
| H A D | tavor_event.c | 102 * EQs to specific interrupts or MSIs XXX in tavor_eq_init_all()
609 * interrupts the bit corresponds to the value in 'inta_pin'. in tavor_isr()
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| /titanic_52/usr/src/cmd/fs.d/ |
| H A D | umount.c | 633 * Try to handle interrupts in a reasonable way. in parumount()
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| /titanic_52/usr/src/uts/intel/io/pci/ |
| H A D | pci_pci.c | 698 "interrupts", -1) != -1) { in ppb_initchild()
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| /titanic_52/usr/src/uts/i86pc/cpu/authenticamd/ |
| H A D | authamd_main.c | 376 * If requested also disable the interrupts taken on counter overflow
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| /titanic_52/usr/src/uts/i86pc/ml/ |
| H A D | cpr_wakecode.s | 234 * - Interrupts are disabled.
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| /titanic_52/usr/src/grub/grub-0.97/netboot/ |
| H A D | eepro100.c | 556 /* Disable interrupts on our PCI board by setting the mask bit */ in eepro100_disable()
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| /titanic_52/usr/src/uts/sun4u/io/ |
| H A D | todds1287.c | 44 * the Fail-safe timer due to limitation in handling interrupts,
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| H A D | sbd_cpu.c | 923 "disable interrupts on cpu %d", in sbd_cancel_cpu()
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| /titanic_52/usr/src/uts/common/io/vioblk/ |
| H A D | vioblk.c | 317 * Now in polling mode. Interrupts are off, so we
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| /titanic_52/usr/src/cmd/bnu/ |
| H A D | perfstat.c | 526 float ticks; /* Clock interrupts per second. */
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| /titanic_52/usr/src/uts/common/crypto/io/ |
| H A D | dca.c | 615 dca_diperror(dip, "hilevel interrupts not supported"); in dca_attach()
789 /* enable interrupts on the device */ in dca_attach()
970 /* disable device interrupts */ in dca_detach()
2492 * disabling of all interrupts from the device. in dca_failure()
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