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/titanic_53/usr/src/uts/common/io/1394/adapters/
H A Dhci1394_isr.c74 "High Level interrupts not supported"); in hci1394_isr_init()
155 * Setup the initial interrupt mask for OpenHCI. These are the interrupts
165 /* start off with all interrupts cleared/disabled */ in hci1394_isr_mask_setup()
191 * interrupts supported in here even if they are not initially enabled
214 * Get all of the enabled 1394 interrupts which are currently in hci1394_isr()
219 /* handle the asserted interrupts */ in hci1394_isr()
327 * See if any of the enabled 1394 interrupts have been asserted in hci1394_isr()
361 * We will disable all interrupts and just return. We shouldn't have in hci1394_isr_bus_reset()
362 * to disable the interrupts, but we will just in case. in hci1394_isr_bus_reset()
473 /* Clear busReset and selfIdComplete interrupts */ in hci1394_isr_self_id()
[all …]
H A Dhci1394_detach.c65 /* Don't allow the HW to generate any more interrupts */ in hci1394_detach()
70 /* Clear any pending interrupts - no longer valid */ in hci1394_detach()
121 /* Don't allow the HW to generate any more interrupts */ in hci1394_detach()
126 /* Clear any pending interrupts - no longer valid */ in hci1394_detach()
189 /* Don't allow the HW to generate any more interrupts */ in hci1394_quiesce()
194 /* Clear any pending interrupts - no longer valid */ in hci1394_quiesce()
/titanic_53/usr/src/boot/sys/boot/fdt/dts/arm/
H A Dyyhd18-m3.dts128 interrupts = <0 72 1>; /* AM_IRQ2(8) */
152 interrupts = <0 28 1>; /* AM_IRQ0(28) */
180 interrupts = <0 30 4>; /* AM_IRQ0(30) */
189 interrupts = <0 31 4>; /* AM_IRQ0(31) */
200 interrupts = <0 8 1>; /* AM_IRQ0(8) */
211 interrupts = <0 2 1>, /* AM_IRQ0(2) */
H A Dexynos5420.dtsi49 interrupts = < 77 110 78 82 79 >;
88 interrupts = <107>;
97 interrupts = <108>;
106 interrupts = <109>;
H A Dodroidc1.dts196 interrupts = <0 72 1>;
243 interrupts = <0 28 1>;
270 interrupts = <0 78 1>;
306 interrupts = <0 30 4>;
317 interrupts = <0 31 4>;
328 interrupts = <0 8 1>;
341 interrupts = <0 2 1>,
H A Dvsatv102-m6.dts155 interrupts = <0 72 1>; /* AM_IRQ2(8) */
202 interrupts = <0 28 1>; /* AM_IRQ0(28) */
239 interrupts = <0 30 4>; /* AM_IRQ0(30) */
248 interrupts = <0 31 4>; /* AM_IRQ0(31) */
259 interrupts = <0 8 1>; /* AM_IRQ0(8) */
272 interrupts = <0 2 1>, /* AM_IRQ0(2) */
/titanic_53/usr/src/man/man9f/
H A Dddi_intr_get_cap.9f88 For discrete interrupts, the host supports \fBedge\fR type of trigger. This
99 For discrete interrupts the host supports \fBlevel\fR, \fBedge\fR, or both
130 All interrupts of the given type must be block-enabled and are not individually
143 The \fBddi_intr_set_cap()\fR function can be called after interrupts are
H A Dddi_intr_add_softint.9f302 \fBExample 1 \fRDevice using high-level interrupts
305 In the following example, the device uses high-level interrupts. High-level
306 interrupts are those that interrupt at the level of the scheduler and above.
307 High-level interrupts must be handled without using system services that
308 manipulate thread or process states, because these interrupts are not blocked
401 /* Enable soft interrupts */
/titanic_53/usr/src/boot/sys/boot/fdt/dts/mips/
H A Dberipad-de4.dts109 interrupts = <0 1 2 3 4>;
119 interrupts = <6>;
126 interrupts = <0>;
200 interrupts = <1 2>;
213 interrupts = <11 12>;
230 interrupts = <4 5>;
H A Dberi-netfpga.dts111 interrupts = <0 1 2 3 4>;
120 interrupts = <0>;
131 interrupts = <8>;
144 interrupts = <1>;
/titanic_53/usr/src/uts/sun4u/serengeti/sys/
H A Dsgsbbc_iosram.h50 #define SBBC_INTR_SC_KEY 3 /* Solaris -> SC Interrupts reason */
51 #define SBBC_SC_INTR_KEY 4 /* SC -> Solaris Interrupts reason */
56 #define SBBC_SC_INTR_ENABLED_KEY 9 /* SC -> Solaris Interrupts */
57 #define SBBC_INTR_SC_ENABLED_KEY 10 /* Solaris -> SC Interrupts */
/titanic_53/usr/src/uts/sun4v/io/
H A Dcnex.c89 * In order to balance interrupts among available CPUs, we use
91 * assign weights to channel interrupts. These weights, which are
95 * Interrupts for VIO devclass channels are given more weight than
96 * other interrupts because they are expected to occur more
98 * Transmit interrupts are given a zero weight because they are
102 * interrupts are redistributed and when they are added. However,
103 * removal of interrupts can unbalance the distribution even if
105 * are added. This can occur when interrupts are removed after
109 * relative to other weighted interrupts on the system. For VIO
314 * framework. This will redirect interrupts at CPUs that are
[all …]
/titanic_53/usr/src/uts/common/sys/
H A Dddi_intr_impl.h45 DDI_INTROP_SUPPORTED_TYPES = 1, /* 1 get supported interrupts types */
46 DDI_INTROP_NINTRS, /* 2 get num of interrupts supported */
53 DDI_INTROP_BLOCKENABLE, /* 9 block enable interrupts */
54 DDI_INTROP_BLOCKDISABLE, /* 10 block disable interrupts */
63 DDI_INTROP_NAVAIL, /* 19 get num of available interrupts */
114 uint_t ih_scratch1; /* Scratch1: #interrupts */
230 int ipool_types; /* Types of interrupts */
268 int iparams_types; /* Types of interrupts in pool */
396 * device. It is used in an array for devices with multiple interrupts.
/titanic_53/usr/src/man/man1m/
H A Dth_define.1m85 applies to all \fBPIO\fR accesses, all interrupts, and all DMA accesses to and
157 accesses, interrupts and DMA accesses to and from areas mapped for both reading
277 interrupts has been requested then the operator may take any of the following
286 next \fIfailcount\fR number of interrupts for \fIoperand\fR number of
296 After \fIcount\fR number of interrupts, fail to deliver the next
297 \fIfailcount\fR number of real interrupts to the driver.
306 After \fIcount\fR number of interrupts, start delivering \fIoperand\fR number
307 of extra interrupts for the next \fIfailcount\fR number of real interrupts.
788 Causes the next six interrupts for instance 3 of the \fBfoo\fR driver to be
796 driver occurs, a further ten interrupts are also generated.
/titanic_53/usr/src/uts/sun/io/
H A Dzs.conf28 reg=0x210,0xf1000000,0x4 interrupts=12;
31 reg=0x210,0xf0000000,0x4 interrupts=12;
36 reg=0x210,0xe0000004,0x4 interrupts=12;
/titanic_53/usr/src/uts/sun4u/serengeti/io/
H A Dsgsbbc.c250 * Verify that an 'interrupts' property exists for in sbbc_attach()
254 DDI_PROP_DONTPASS, "interrupts", in sbbc_attach()
256 SBBC_ERR1(CE_WARN, "No 'interrupts' property for the " in sbbc_attach()
308 * Enable Interrupts now, turn on both INT#A lines in sbbc_attach()
388 * Disable Interrupts now, turn OFF both INT#A lines in sbbc_detach()
612 if (intr_reason == 0) /* No more interrupts to be processed */ in sbbc_intr_handler()
711 * Verify that an 'interrupts' property in sbbc_chosen_init()
716 DDI_PROP_DONTPASS, "interrupts", in sbbc_chosen_init()
719 SBBC_ERR(CE_PANIC, "No 'interrupts' property for the " in sbbc_chosen_init()
941 * map in the SBBC interrupts in sbbc_add_intr()
[all …]
/titanic_53/usr/src/uts/i86pc/io/apix/
H A Dapix_intr.c110 * If there is blocked higher level interrupts, return in apix_remove_pending_av()
131 * Add hardware interrupts to the interrupt pending list.
177 * Walk pending hardware interrupts at given priority level, invoking
200 /* Don't enable interrupts during x-calls */ in apix_dispatch_pending_autovect()
335 * If there are pending interrupts, send a softint to in apix_do_softint_epilog()
384 * Called with interrupts disabled.
474 * To support reentrant level 15 interrupts, we maintain a in apix_hilevel_intr_prolog()
505 * To support reentrant level 15 interrupts, we maintain a in apix_hilevel_intr_epilog()
592 * High priority interrupts run on this cpu's interrupt stack. in apix_do_pending_hilevel()
609 * The IF flag is cleared and thus all maskable interrupts are blocked at
[all …]
/titanic_53/usr/src/uts/common/io/chxge/com/
H A Dmv88e1xxx.c93 /* Enable PHY interrupts. */ in mv88e1xxx_interrupt_enable()
97 /* Enable Marvell interrupts through Elmer0. */ in mv88e1xxx_interrupt_enable()
113 /* Disable all phy interrupts. */ in mv88e1xxx_interrupt_disable()
116 /* Disable Marvell interrupts through Elmer0. */ in mv88e1xxx_interrupt_disable()
134 /* Clear PHY interrupts by reading the register. */ in mv88e1xxx_interrupt_clear()
137 /* Clear Marvell interrupts through Elmer0. */ in mv88e1xxx_interrupt_clear()
323 * Loop until cause reads zero. Need to handle bouncing interrupts. in mv88e1xxx_interrupt_handler()
/titanic_53/usr/src/uts/common/io/usb/hcd/uhci/
H A Duhci.c369 /* Enable all interrupts */ in uhci_attach()
380 /* Call ddi_intr_block_enable() for MSI interrupts */ in uhci_attach()
384 /* Call ddi_intr_enable for MSI or FIXED interrupts */ in uhci_attach()
437 * Set HcInterruptEnable to enable all interrupts except Root in uhci_attach()
438 * Hub Status change and SOF interrupts. in uhci_attach()
445 "No SOF interrupts have been received, this USB UHCI host" in uhci_attach()
481 * Register FIXED or MSI interrupts.
493 /* Get number of interrupts */ in uhci_add_intrs()
503 /* Get number of available interrupts */ in uhci_add_intrs()
660 * Unregister FIXED or MSI interrupts
[all …]
/titanic_53/usr/src/uts/i86pc/io/
H A Dhpet_acpi.c291 * Note: FSB (MSI) interrupts are not currently supported by Intel HPETs as of
627 * The HPET timers specify which I/O APIC interrupts they can be routed to.
703 * Callers must block interrupts before calling this function if they must
783 * disable the timer from generating interrupts here.
999 * Interrupt Service Routine for HPET I/O-APIC-generated interrupts.
1031 * structures before enabling timer interrupts. ASSERT the software in hpet_isr()
1037 * CPUs in deep c-states do not enable interrupts until after in hpet_isr()
1045 * Higher level interrupts may deadlock with CPUs going idle if this in hpet_isr()
1158 * Idle CPUs disable interrupts before programming the in hpet_guaranteed_schedule()
1160 * interrupts the idle cpu before it can enter a in hpet_guaranteed_schedule()
[all …]
/titanic_53/usr/src/uts/common/io/xge/hal/xgehal/
H A Dxgehal-device-fp.c145 * interrupt was raised by the device. Next, it masks the device interrupts.
149 * bridge. Therefore, two back-to-back interrupts are potentially possible.
508 * xge_hal_device_mask_tx - Mask Tx interrupts.
511 * Mask Tx device interrupts.
527 * xge_hal_device_mask_rx - Mask Rx interrupts.
530 * Mask Rx device interrupts.
546 * xge_hal_device_mask_all - Mask all device interrupts.
549 * Mask all device interrupts.
564 * xge_hal_device_unmask_tx - Unmask Tx interrupts.
567 * Unmask Tx device interrupts.
[all …]
/titanic_53/usr/src/uts/sun4u/io/pci/
H A Dpci_ib.c143 * can only used for psycho internal interrupts thermal, power,
173 * Can only be used for internal interrupts: thermal, power, ue, ce, pbm.
211 /* can only used for psycho internal interrupts thermal, power, ue, ce, pbm */
220 * distribute PBM and UPA interrupts. ino is set to 0 by caller if we
221 * are dealing with UPA interrupts (without inos).
325 * Redistribute interrupts of the specified weight. The first call has a weight
400 * heavy weighted interrupts first (across all nexus driver in ib_intr_dist_all()
457 * Reset interrupts to IDLE. This function is called during
458 * panic handling after redistributing interrupts; it's needed to
472 * Note that we only actually care about interrupts that are in ib_intr_reset()
[all …]
/titanic_53/usr/src/man/man9s/
H A Dkstat_intr.9s46 Drivers generally report only claimed hard interrupts and soft interrupts from
47 their handlers, but measurement of the spurious class of interrupts is useful
/titanic_53/usr/src/uts/sun4u/os/
H A Dmach_cpu_states.c62 * we are in a normal shutdown sequence (interrupts are not blocked, the
92 * 2) wait for pending interrupts prior to redistribution in mdboot()
279 * we disable further %tick_cmpr interrupts. If not, an explicit call to panic
281 * further level 14 interrupts to be processed once we lower PIL. This allows
360 * Redirect all interrupts to the current CPU. in panic_quiesce_hw()
369 * platforms, interrupts may have arrived while we were in panic_quiesce_hw()
370 * stopped in OBP. OBP will arrange for those interrupts to in panic_quiesce_hw()
373 * (network swap devices), we need interrupts to be in panic_quiesce_hw()
/titanic_53/usr/src/uts/common/io/bnxe/
H A Dbnxe.conf247 # rx_interrupt_coalesce_usec - time between rx interrupts in usecs
255 # tx_interrupt_coalesce_usec - time between tx interrupts in usecs
263 # disable_msix - turn off MSI-X and use Fixed level interrupts
430 # allocation limit of MSIX interrupts. By default, Solaris limits each driver
432 # only a maximum of 31 MSIX interrupts are available per interrupt priority
439 # resulting in interrupts never being received on the interface which reverted
442 # To ensure all interfaces are able to allocate their two MSIX interrupts, the
486 # % echo "::interrupts -d" | mdb -k

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