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/titanic_50/usr/src/lib/libshell/common/
H A Dshell.3348 to execute, then it should check for interrupts
/titanic_50/usr/src/grub/grub-0.97/netboot/
H A Dpci.c491 * %PCI_CAP_ID_MSI Message Signalled Interrupts
H A Dundi.c948 * interrupts. We therefore cheat and pretend that an in undi_poll()
974 * appear to combine interrupts. If we loop through GET_NEXT, in undi_poll()
1011 * interrupts. Move on to next frame. in undi_poll()
H A Dtlan.c350 /* 2. Turn off interrupts. ( Probably isn't necessary ) */ in TLan_ResetAdapter()
784 * This disables DMA and interrupts so we don't receive in tlan_disable()
785 * unexpected packets or interrupts from the card after in tlan_disable()
797 IRQ - Enable, Disable, or Force interrupts
H A Ddavicom.c625 /* disable interrupts */ in davicom_disable()
637 /* eth_irq - enable, disable and force interrupts */
/titanic_50/usr/src/uts/common/pcmcia/nexus/
H A Dpcmcia.c769 { "interrupts", sizeof (int), PCMCIA_PROP_INTR },
1479 /* disable interrupts at this point */ in pcm_adapter_callback()
3263 "interrupts", ppd->ppd_intr); in pcmcia_init_devinfo()
3561 * interrupts need a little work. For x86, the valid IRQs will in SSInquireAdapter()
4139 * While some adapters share interrupts at the lowest
4143 * the arg is a pcmcia_socket structure and all interrupts
5019 /* PCI nexus driver supports only fixed interrupts */ in pcmcia_intr_ops()
5057 DDI_PROP_DONTPASS, "interrupts", -1) < 0)) in pcmcia_intr_get_ispec()
5274 /* Enable interrupts */ in pcmcia_intr_enable_isr()
/titanic_50/usr/src/uts/common/io/mac/
H A Dmac_sched.c102 * interrupts for transmit being completed.
136 * spreading the incoming receive load out across multiple interrupts which
347 * (mblk_t chain) during the context of a single interrupt. However, interrupts
354 * (disable) interrupts on that specific ring and the polling thread will start
359 * polling on the hardware ring will be quiesced and interrupts will be
362 * device as opposed to relying on interrupts can actually reduce overall system
366 * idea here is that we do not disable interrupts on the device as a whole, but
2415 * interrupts off but not polling the H/W. The in mac_rx_srs_poll_ring()
2553 * The first thing we do is disable interrupts if possible and then
2793 * The first thing we do is disable interrupts if possible and then
/titanic_50/usr/src/uts/common/io/iwh/
H A Diwh.c636 "no fixed interrupts\n"); in iwh_attach()
2852 * re-enable interrupts in iwh_rx_softintr()
2888 * disable interrupts in iwh_intr()
2893 * ack interrupts in iwh_intr()
2943 * re-enable interrupts in iwh_intr()
4519 * Disable and mask all interrupts. in iwh_quiesce()
4585 * clear any pending interrupts in iwh_preinit()
4938 * disable interrupts in iwh_stop()
5675 * clear any pending interrupts in iwh_init_common()
5680 * enable interrupts in iwh_init_common()
/titanic_50/usr/src/uts/common/io/e1000g/
H A De1000g_tx.c215 * Transmit interrupt delay can produce Transmit interrupts little in e1000g_send()
437 * Enable Transmit interrupts, so that the interrupt routine can in e1000g_send()
466 * Enable Transmit interrupts, so that the interrupt routine can in e1000g_send()
/titanic_50/usr/src/uts/sun4v/ml/
H A Dmach_locore.s738 ! disable interrupts and check for ASTs and wbuf restores
1394 ! Pending interrupts is also cleared in order to avoid a recursive call
1491 ! enable limited interrupts
/titanic_50/usr/src/uts/common/io/cardbus/
H A Dcardbus.c1284 "interrupts", -1) != -1) in cardbus_initchild()
2243 cardbus_err(dip, 1, "Only fixed interrupts\n"); in cardbus_intr_ops()
2291 cardbus_err(dip, 1, "Only fixed interrupts\n"); in cardbus_enable_intr_impl()
2327 cardbus_err(dip, 1, "Only fixed interrupts\n"); in cardbus_disable_intr_impl()
/titanic_50/usr/src/uts/i86xpv/os/
H A Dxpv_panic.c541 * Be prepared to absorb any stray device interrupts received in switch_to_xpv_panic_idt()
615 xpv_panic_printf("%d unexpected interrupts received.\n", cnt); in xpv_interrupt()
/titanic_50/usr/src/uts/intel/ia32/os/
H A Dsundep.c442 * (This means that we need to have interrupts disabled when we test
444 * to keep interrupts disabled until we return to userland so we can't
/titanic_50/usr/src/uts/common/xen/io/
H A Dxenbus_xs.c1034 * We have to wait for interrupts to be ready, so we don't clash in xenbus_thread()
1054 * event channel; start xenbus threads for responding to interrupts.
/titanic_50/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/
H A Dlm_mcp.c582 …e we will only get a response from the MCP when it's done). We don't need a lock because interrupts in lm_loader_lock()
691 …e we will only get a response from the MCP when it's done). We don't need a lock because interrupts in lm_loader_unlock()
/titanic_50/usr/src/uts/common/io/i40e/
H A Di40e_gld.c501 * We only provide the handle in cases where we have MSI-X interrupts, in i40e_fill_tx_ring()
539 * We only provide the handle in cases where we have MSI-X interrupts, in i40e_fill_rx_ring()
/titanic_50/usr/src/uts/common/io/drm/
H A DdrmP.h794 /* number of VBLANK interrupts */
802 /* number of users of vblank interrupts per crtc */
/titanic_50/usr/src/uts/sun4/io/px/
H A Dpx_fm.c472 * Note on pfd: Different interrupts will populate the pfd's differently. The
512 * If a cpu trap does occur, it will quiesce all other interrupts allowing
/titanic_50/usr/src/man/man3cpc/
H A Dcpc_bind_curlwp.3cpc508 measured. Less frequent interrupts and samples lead to less perturbation of the
/titanic_50/usr/src/uts/i86xpv/sys/
H A Dmachprivregs.h308 * Used to re-enable interrupts in the body of exception handlers
/titanic_50/usr/src/uts/common/io/arn/
H A Darn_beacon.c200 /* NB: don't enable any interrupts */ in arn_beaconq_setup()
/titanic_50/usr/src/uts/sun4u/io/
H A Dmach_rootnex.c134 * Interrupts from the slave UPA devices are in rootnex_add_intr_impl()
/titanic_50/usr/src/cmd/svr4pkg/pkginstall/
H A Dquit.c240 /* disable interrupts */ in quit()
/titanic_50/usr/src/cmd/backup/dump/
H A Ddumpoptr.c215 * Here if an inquisitive operator interrupts the dump program
/titanic_50/usr/src/uts/common/io/ipw/
H A Dipw2100_hw.c473 * enable all interrupts in ipw2100_load_fw()

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