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/titanic_52/usr/src/uts/common/io/bge/
H A Dbge_recv2.c337 * Once the ring interrupts are disabled, we need to do bge_recyle()
340 * have MSI-X interrupts support for this.
H A Dbge_main2.c463 * Start chip processing, including enabling interrupts in bge_start()
3708 * accesses, but with interrupts and Bus Mastering off.
3712 * and allow interrupts only when everything else is set up.
3911 * interrupts ...
3965 bge_error(bgep, "No interrupts registered\n");
3970 * Note that interrupts are not enabled yet as
3986 * Now that mutex locks are initialized, enable interrupts.
4358 * Register FIXED or MSI interrupts.
4369 /* Get number of interrupts */
4378 /* Get number of available interrupts */
[all...]
/titanic_52/usr/src/boot/sys/boot/efi/loader/arch/amd64/
H A Dtrap.c51 * This code catches exceptions but forwards hardware interrupts to
53 * vs. interrupts by presence of the error code on the stack, which
/titanic_52/usr/src/uts/common/sys/
H A Dprocessor.h69 #define P_NOINTR 0x0006 /* processor is online, but no I/O interrupts */
/titanic_52/usr/src/man/man9e/
H A Dattach.9e57 driver. Device interrupts are not blocked when attaching a device to the
/titanic_52/usr/src/uts/common/io/hxge/
H A Dhxge.conf45 # Interrupts after this number of NIU hardware ticks have
/titanic_52/usr/src/uts/common/io/ntxn/
H A Dnx_hw_pci_regs.h60 * Message Signaled Interrupts
/titanic_52/usr/src/lib/libbc/inc/include/
H A Dmntent.h70 #define MNTOPT_INTR "intr" /* allow interrupts on hard mount */
/titanic_52/usr/src/uts/common/io/chxge/
H A Dsge.c286 /* wait until there's no more outstanding interrupts pending */ in sge_stop()
502 * Disable SGE error interrupts.
518 * Enable SGE error interrupts.
535 * Clear SGE error interrupts.
741 /* handle non-data interrupts */ in sge_data_in()
1149 /* Clear the F_FL_EXHAUSTED interrupts for now */ in freelQs_empty()
1599 * Assumes that SGE is stopped and all interrupts are disabled.
/titanic_52/usr/src/uts/sun/sys/dada/impl/
H A Dudcd.h106 #define UDCD_NOINTR 0x00040 /* No interrupts */
/titanic_52/usr/src/uts/intel/sys/acpi/platform/
H A Dacwin.h78 * 2) Interrupts are turned off during ACPI register setup
H A Daclinuxex.h82 * Interrupts are off during resume, just like they are for boot.
/titanic_52/usr/src/man/man3c/
H A Daio_suspend.3c30 has completed, until a signal interrupts the function, or, if \fItimeout\fR is
/titanic_52/usr/src/grub/grub-0.97/netboot/
H A Dforcedeth.c882 * This disables DMA and interrupts so we don't receive in forcedeth_disable()
883 * unexpected packets or interrupts from the card after in forcedeth_disable()
895 /* disable interrupts on the nic or we will lock up */ in forcedeth_disable()
908 IRQ - Enable, Disable, or Force interrupts
H A Dpci.h163 #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
228 /* Message Signalled Interrupts registers */
/titanic_52/usr/src/uts/common/io/arn/
H A Darn_core.h247 uint32_t ast_hardware; /* fatal hardware error interrupts */
248 uint32_t ast_rxorn; /* rx overrun interrupts */
249 uint32_t ast_rxeol; /* rx eol interrupts */
250 uint32_t ast_txurn; /* tx underrun interrupts */
/titanic_52/usr/src/uts/common/io/audio/drv/audiopci/
H A Daudiopci.c314 /* Set # of frames between interrupts */ in audiopci_init_port()
339 /* Set # of frames between interrupts */ in audiopci_init_port()
365 /* Set # of frames between interrupts */ in audiopci_init_port()
1308 /* This disables all DMA engines and interrupts */ in audiopci_quiesce()
/titanic_52/usr/src/cmd/format/
H A Dmisc.c337 * Lock out interrupts to avoid recursion. in cleanup()
384 * critical zone, no interrupts are allowed. Note that calls to this
393 * If there is no saved environment, interrupts will be ignored. in enter_critical()
/titanic_52/usr/src/uts/i86pc/os/
H A Dtimestamp.c241 * We need to disable interrupts here to assure that we in tsc_gethrtime_delta()
301 * Interrupts are disabled to ensure that the thread isn't in dtrace_gethrtime()
350 * Again, disable interrupts to ensure that the thread in dtrace_gethrtime()
/titanic_52/usr/src/contrib/ast/src/lib/libcmd/
H A DRELEASE2 12-06-19 tail.c: be nice and use sh_sigcheck() and tvsleep() to verify interrupts
64 09-06-18 rm.c: handle interrupts during interactive query
65 09-06-18 cp.c: handle interrupts during interactive query
/titanic_52/usr/src/uts/common/io/zyd/
H A Dzyd_hw.c502 /* disable interrupts */ in zyd_hw_configure()
662 /* enable interrupts */ in zyd_hw_start()
697 /* disable interrupts */ in zyd_hw_stop()
/titanic_52/usr/src/uts/common/io/nxge/
H A Dnxge_main.c45 * may generate spurious interrupts after the
373 * interrupts to spread the interrupts among
378 * The default number of MSI interrupts are set to
1029 * Stop any further interrupts. in nxge_unattach()
1481 "==> nxge_unmap_regs: device interrupts")); in nxge_unmap_regs()
3831 * Enable hardware interrupts. in nxge_m_start()
3838 * In guest domain we enable RDCs and their interrupts as in nxge_m_start()
3905 * Disable hardware interrupts. in nxge_m_stop()
6004 "interrupts registere in nxge_add_intrs()
[all...]
/titanic_52/usr/src/uts/sun4/ml/
H A Dsubr_asm.s134 * disable interrupts, clear Address Mask to access 64 bit physaddr
151 * disable interrupts, clear Address Mask to access 64 bit physaddr
/titanic_52/usr/src/uts/sun4v/sys/
H A Dqcn.h95 ddi_intr_handle_t *qcn_htable; /* For array of interrupts */
/titanic_52/usr/src/cmd/lp/cmd/
H A Dlpshut.c52 * protected from interrupts. We do want to catch them, however,

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