| /titanic_52/usr/src/uts/intel/io/scsi/adapters/arcmsr/ |
| H A D | arcmsr.c | 300 * Add interrupts needed.
2417 /* Determine number of supported interrupts */ in arcmsr_add_intr()
2421 "no interrupts of type %s, rc=0x%x, count=%d", in arcmsr_add_intr()
2435 arcmsr_log(acb, CE_NOTE, "Got %d interrupts, but requested %d", in arcmsr_add_intr()
2479 /* Disable all interrupts */ in arcmsr_remove_intr()
3229 /* disable all outbound interrupts */ in arcmsr_abort_dr_ccbs()
3467 /* disable all interrupts */ in arcmsr_disable_allintr()
3609 /* clear interrupts */ in arcmsr_hba_wait_msgint_ready()
3646 /* clear interrupts */ in arcmsr_hbb_wait_msgint_ready()
3685 /* clear interrupts */ in arcmsr_hbc_wait_msgint_ready()
[all...] |
| /titanic_52/usr/src/uts/common/io/cxgbe/common/ |
| H A D | t4_hw.c | 1608 * interrupts described by the mask have occured. The actions include
1634 if (status != 0) /* clear processed interrupts */ in t4_handle_intr_status()
2189 * data interrupts typically don't involve any MMIOs.
2243 /* Clear the interrupts just processed for which we are the master. */ in t4_slow_intr_handler()
2250 * t4_intr_enable - enable interrupts
2251 * @adapter: the adapter whose interrupts should be enabled
2253 * Enable PF-specific interrupts for the calling function and the top-level
2254 * interrupt concentrator for global interrupts. Interrupts are already
2259 * non PF-specific interrupts fro
[all...] |
| /titanic_52/usr/src/uts/sun/sys/scsi/adapters/ |
| H A D | fasdma.h | 59 #define DMA_INTEN 0x0010 /* (RW) enable interrupts */
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| /titanic_52/usr/src/uts/intel/sys/acpi/platform/ |
| H A D | acwin64.h | 61 * 2) Interrupts are turned off during ACPI register setup
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| /titanic_52/usr/src/uts/common/io/ |
| H A D | ecpp.conf | 90 # name="lp" parent="/isa" interrupts=7 reg=1,0x378,0x8;
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| /titanic_52/usr/src/uts/common/sys/ |
| H A D | mutex.h | 58 MUTEX_SPIN = 1, /* block interrupts and spin */
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| H A D | mac_soft_ring.h | 226 * reenable the interrupts.
244 /* Drain is done and interrupts are reenabled */
271 * The polling works by turning off interrupts as soon as a packets
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| /titanic_52/usr/src/uts/common/inet/ |
| H A D | squeue.c | 106 * doesn't keep getting disturbed by high priority interrupts. As part
108 * the interrupts and switches to poll mode. In poll mode, when poll
761 * just disable the interrupts for drain by non worker (kernel in squeue_drain()
855 * We turn off interrupts for all userland threads in squeue_drain()
890 * turn the interrupts back on and we are done. in squeue_drain()
1011 * Avoiding deadlocks with interrupts
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| /titanic_52/usr/src/uts/common/io/rtls/ |
| H A D | rtls.c | 391 * we don't support high level interrupts in the driver in rtls_attach()
487 * This will prevent receiving interrupts before device is ready, as in rtls_attach()
488 * we are initializing device after setting the interrupts. So we in rtls_attach()
1197 * Called when receive interrupts detected
1436 /* no need to hand other interrupts */ in rtls_intr()
1765 * No early-rx interrupts in rtls_chip_init()
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| /titanic_52/usr/src/uts/i86pc/ml/ |
| H A D | locore.s | 79 * - Interrupts are disabled.
380 * mask out all interrupts so that ISR will not change
906 * infinitum. The undesirable effect of this situation is that interrupts are
1141 * reenable interrupts. (In the case of pagefaults, we enter through an
1242 * reenable interrupts. (In the case of pagefaults, we enter through an
1571 CLI(%rax) /* disable interrupts */
1672 CLI(%eax) /* disable interrupts */
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| /titanic_52/usr/src/uts/sun4u/io/pci/ |
| H A D | pci_ecc.c | 131 * Disable UE and CE ECC error interrupts. in ecc_destroy()
600 * re-enable CE interrupts if no more CEs are detected. in ecc_err_drain()
635 * If no more CE errors are found then enable interrupts(by in ecc_delayed_ce()
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| /titanic_52/usr/src/uts/intel/ia32/os/ |
| H A D | fpu.c | 430 * Now we can enable the interrupts. in fpnoextflt()
527 * Now we can enable the interrupts. in fpexterrflt()
602 * NOTE: Interrupts are disabled during execution of this in fpsimderrflt()
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| /titanic_52/usr/src/uts/i86pc/io/pci/ |
| H A D | pci.c | 700 * If the "interrupts" property doesn't exist, in pci_initchild()
705 DDI_PROP_DONTPASS, "interrupts", -1) == -1) in pci_initchild()
728 "interrupts", -1) != -1) in pci_initchild()
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| /titanic_52/usr/src/uts/common/sys/nxge/ |
| H A D | nxge.h | 481 boolean_t intr_registered; /* interrupts are registered */
482 boolean_t intr_enabled; /* interrupts are enabled */
492 ddi_intr_handle_t *htable; /* For array of interrupts */
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| /titanic_52/usr/src/uts/common/io/igb/ |
| H A D | igb_sw.h | 185 #define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */
192 #define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */
329 igb_nic_func_t enable_intr; /* enable adapter interrupts */
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| /titanic_52/usr/src/uts/common/io/ipw/ |
| H A D | ipw2100.c | 603 * stop the hardware; this mask all interrupts in ipw2100_cpr_suspend()
667 * enable all interrupts in ipw2100_cpr_resume()
707 * Disable and mask all interrupts. in ipw2100_quiesce()
1233 * all ipw2100 interrupts will be masked by this routine
1242 * disable interrupts in ipw2100_master_stop()
1265 * all ipw2100 interrupts will be masked by this routine
2688 * mask all interrupts in ipw2100_intr()
2693 * acknowledge all fired interrupts in ipw2100_intr()
2868 * enable all interrupts in ipw2100_intr()
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| /titanic_52/usr/src/man/man9f/ |
| H A D | mkiocb.9f | 235 8 /* Handle interrupts */
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| /titanic_52/usr/src/uts/sun4v/os/ |
| H A D | cpc_subr.c | 72 * Prepare for CPC interrupts and install an idle thread CPC context.
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| /titanic_52/usr/src/uts/i86pc/sys/ |
| H A D | machprivregs.h | 54 * Used to re-enable interrupts in the body of exception handlers
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| /titanic_52/usr/src/uts/common/io/aac/ |
| H A D | README | 72 MSI interrupts supporting is added in this release:
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| /titanic_52/usr/src/boot/sys/boot/fdt/dts/arm/ |
| H A D | digi-ccwmx53.dts | 117 interrupts = <0x1 0x1 0 0>;
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| /titanic_52/usr/src/boot/sys/boot/efi/loader/arch/amd64/ |
| H A D | multiboot_tramp.S | 35 * interrupts disabled
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| /titanic_52/usr/src/uts/common/os/ |
| H A D | cpu.c | 623 * . interrupts have already bypassed this case (see above) in thread_nomigrate()
781 * because that might block clock interrupts needed in cpu_pause()
788 * to block out all interrupts below LOCK_LEVEL so that in cpu_pause()
1099 * Determine whether the CPU is online and handling interrupts.
1129 * Determine whether the CPU is handling interrupts.
1312 * shut off interrupts on the CPU, don't quiesce it, but don't in cpu_offline()
1346 * to give short-lived threads (such as interrupts) chance to in cpu_offline()
1348 * is required to service interrupts, then we take the route in cpu_offline()
1412 * all outstanding low-level interrupts run to completion in cpu_offline()
1546 * If we failed, re-enable interrupts in cpu_offline()
[all...] |
| H A D | ftrace.c | 107 * interrupts temporarily. This approach makes the least assumption about the
352 * added precaution, we call these before we disable interrupts on this cpu.
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| /titanic_52/usr/src/cmd/mdb/i86pc/modules/common/ |
| H A D | intr_common.c | 179 * d1/d3 are cbe_fire interrupts
376 /* shared interrupts with one or more ISR removed afterwards */ in apix_interrupt_dump()
|