| /titanic_52/usr/src/uts/sparc/v9/ml/ |
| H A D | ddi_v9_asm.s | 1162 * on_trap. In the case of a peek, we may also need to re-enable interrupts.
1179 andcc %o3, PSTATE_IE, %g0 ! enable interrupts
1249 * - re-enable interrupts if neccessary
1270 andcc %o3, PSTATE_IE, %g0 ! enable interrupts
1329 andcc %o3, PSTATE_IE, %g0 ! enable interrupts
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| /titanic_52/usr/src/grub/grub-0.97/netboot/ |
| H A D | sis900.c | 618 * Description: disables interrupts and soft resets the controller chip
1129 /* Disable interrupts by clearing the interrupt mask. */ in sis900_transmit()
1194 * Description: Turns off interrupts and stops Tx and Rx engines
1208 /* Disable interrupts by clearing the interrupt mask. */ in sis900_disable()
1218 * Description: Enable, Disable, or Force, interrupts
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| /titanic_52/usr/src/uts/common/io/usb/hcd/ehci/ |
| H A D | ehci.c | 288 /* Register interrupts */ in ehci_attach()
671 * We could have gotten a spurious interrupts. If so, do not in ehci_intr()
714 /* VIA VT6202 looses EHCI_INTR_USB interrupts, workaround. */ in ehci_intr()
743 * process any missed USB transaction completion interrupts. in ehci_intr()
752 /* Clear missed interrupts */ in ehci_intr()
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| /titanic_52/usr/src/uts/i86pc/os/ |
| H A D | mp_startup.c | 361 * to drop to 0 (allowing device interrupts before we're ready) in in mp_cpu_configure_common()
1665 * interrupts, cmn_err, etc. Before we can do that, we want to in mp_startup_common()
1716 * Enable interrupts with spl set to LOCK_LEVEL. LOCK_LEVEL is the in mp_startup_common()
1720 * device interrupts that may end up in the hat layer issuing cross in mp_startup_common()
1827 /* Enable interrupts */ in mp_startup_common()
1938 * Take the specified CPU out of participation in interrupts.
1951 * Allow the specified CPU to participate in interrupts.
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| /titanic_52/usr/src/uts/common/io/ib/adapters/tavor/ |
| H A D | tavor.c | 949 /* Teardown Tavor interrupts */ in tavor_drv_fini()
3261 * fallback to using legacy interrupts. Also, if MSI allocatis chosen, in tavor_intr_or_msi_init()
3263 * interrupts. in tavor_intr_or_msi_init()
3289 * Neither MSI or legacy interrupts were successful. return failure. in tavor_intr_or_msi_init()
3306 /* Get number of interrupts/MSI supported */ in tavor_add_intrs()
3316 /* Get number of available interrupts/MSI */ in tavor_add_intrs()
3423 /* Disable Tavor interrupts */
3434 * Check if MSI interrupts are used. If so, disable MSI interupts. in tavor_intr_disable()
3435 * If not, since Tavor doesn't support MSI-X interrupts, assuming the in tavor_intr_disable()
3461 /* Disable MSI interrupts */ in tavor_intr_disable()
[all...] |
| /titanic_52/usr/src/uts/sun4u/sunfire/io/ |
| H A D | fhc.c | 85 * 1-15, and have been modeled after the sun4d interrupts. The mondo
512 * We rely on only using FHC interrupts from one board only
513 * (the UART and SYS interrupts) so that the values of the other IGNs
538 /* We must now re-issue any pending interrupts. */ in fhc_handle_imr()
1143 /* We don't use the two spare interrupts. */ in fhc_add_intr_impl()
1150 /* TOD and Fan Fail interrupts are not usable */ in fhc_add_intr_impl()
1204 * and enable interrupts for this ino. in fhc_add_intr_impl()
1280 * Since all FHC interrupts are level interrupts, any in fhc_add_intr_impl()
1471 /* only support fixed interrupts */ in fhc_intr_ops()
[all...] |
| /titanic_52/usr/src/man/man9f/ |
| H A D | ddi_fm_ereport_post.9f | 100 A leaf device sends too many consecutive interrupts with no work to do.
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| H A D | ddi_intr_add_handler.9f | 197 If a device driver that uses \fBMSI\fR and \fBMSI-X\fR interrupts resets the
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| H A D | semaphore.9f | 147 is used from interrupt context, lower-priority interrupts will not be serviced
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| /titanic_52/usr/src/man/man3c/ |
| H A D | aio_waitn.3c | 23 interrupts the function, or if \fItimeout\fR is not \fINULL\fR, until the time
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| /titanic_52/usr/src/uts/common/sys/ |
| H A D | avintr.h | 83 /* softing contains a bit field of software interrupts which are pending */
|
| H A D | pic.h | 59 #define PIC_VECTBASE 0x20 /* Vectors for external interrupts */
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| H A D | ddi_impldefs.h | 75 DDI_CB_INTR_ADD, /* More available interrupts */
76 DDI_CB_INTR_REMOVE /* Fewer available interrupts */
101 * devi_parent_data includes property lists (interrupts, registers, etc.)
772 int par_nintr; /* number of interrupts */
773 struct intrspec *par_intr; /* array of possible interrupts */
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| /titanic_52/usr/src/uts/sun4u/os/ |
| H A D | cpc_subr.c | 73 * Prepare for CPC interrupts and install an idle thread CPC context.
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| /titanic_52/usr/src/lib/libfakekernel/common/sys/ |
| H A D | mutex.h | 55 MUTEX_SPIN = 1, /* block interrupts and spin */
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| /titanic_52/usr/src/boot/sys/boot/i386/libi386/ |
| H A D | amd64_tramp.S | 76 /* Be sure that interrupts are disabled */
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| /titanic_52/usr/src/uts/common/io/hme/ |
| H A D | hme_mac.h | 189 #define HMEG_STATUS_NORMAL_INT 0x01810000 /* normal interrupts */
191 #define HMEG_STATUS_INTR 0xfefffefc /* All interesting interrupts */
242 /* uninteresting interrupts */
245 * Interrupts which are not interesting are:
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| /titanic_52/usr/src/uts/intel/io/scsi/adapters/pvscsi/ |
| H A D | pvscsi.c | 865 * concurrently before we have actually disabled interrupts. in pvscsi_poll_cmd()
876 /* Disable interrupts from H/W */ in pvscsi_poll_cmd()
900 /* Enable interrupts from H/W */ in pvscsi_poll_cmd()
904 /* No interrupts seen from device during the timeout */ in pvscsi_poll_cmd()
1471 /* Unmask interrupts */ in pvscsi_enable_intrs()
1547 "!failed to get number of available interrupts of type %d", in pvscsi_register_isr()
1563 dev_err(pvs->dip, CE_WARN, "!failed to allocate %d interrupts", in pvscsi_register_isr()
2468 dev_err(pvs->dip, CE_WARN, "!failed to enable interrupts"); in pvscsi_attach()
2589 /* Mask all interrupts from device */ in pvscsi_quiesce()
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| /titanic_52/usr/src/uts/common/io/hxge/ |
| H A D | hxge_main.c | 551 * Enable interrupts. in hxge_attach()
694 /* Stop interrupts. */ in hxge_unattach()
697 /* Stop any further interrupts. */ in hxge_unattach()
883 "==> hxge_unmap_regs: device interrupts")); in hxge_unmap_regs()
1024 * Enable hardware interrupts. in hxge_init()
3722 "interrupts registered : type %d", type)); in hxge_add_intrs()
3735 "==> hxge_add_intrs: failed to register interrupts")); in hxge_add_intrs()
3878 /* Free already allocated interrupts */ in hxge_add_intrs_adv_type()
3893 /* Free already allocated interrupts */ in hxge_add_intrs_adv_type()
4028 /* Free already allocated interrupts */ in hxge_add_intrs_adv_type_fix()
[all...] |
| H A D | hxge_tdc_hw.h | 363 * interrupts, enable mb, send a single marked packet, wait for Ldf0,
364 * clear marked, repeat or 2) disable interrupts, never enable mb,
366 * state, clear marked/mMarked bits, repeat. If interrupts are
1140 * interrupts without needing to create the actual events. This
1179 * debug creation of interrupts without needing to create the actual
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| /titanic_52/usr/src/uts/common/io/chxge/com/ |
| H A D | tp.c | 331 /* We don't use any TP interrupts */ in t1_tp_intr_enable()
376 /* FPGA doesn't support TP interrupts. */ in t1_tp_intr_handler()
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| /titanic_52/usr/src/uts/common/io/cpqary3/ |
| H A D | cpqary3.h | 299 * Hardware & Software Interrupts, Cookies & Mutex.
331 * 0x34 Outbound Interrupt Mask - for masking Interrupts to host
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| /titanic_52/usr/src/uts/sun/sys/ |
| H A D | ser_zscc.h | 52 * nobody interrupts you in between.
77 * of the setting of WR9_VIS.) If no interrupts are pending, the modified
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| /titanic_52/usr/src/uts/intel/sys/acpi/ |
| H A D | acrestyp.h | 185 UINT8 Interrupts[1]; member
426 UINT32 Interrupts[1]; member
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| /titanic_52/usr/src/uts/common/sys/scsi/adapters/mpt_sas/ |
| H A D | mptsas_var.h | 732 * variables for helper threads (fan-out interrupts)
877 ddi_intr_handle_t *m_htable; /* For array of interrupts */
1156 * Mask all interrupts to disable
1163 * Mask Doorbell and Reset interrupts to enable reply desc int.
1427 #define NDBG6(args) MPTSAS_DBGPR(0x40, args) /* interrupts */
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