| /titanic_51/usr/src/uts/i86xpv/os/ |
| H A D | mp_xen.c | 35 * P_ONLINE: the VCPU is up and running, taking interrupts and running threads
39 * receive interrupts, and we require this for offline CPUs in Solaris.
42 * xen_vcpu_down() for it). It can't take interrupts or run anything, though
65 * state: it must have a saved PCB, and not be responding to interrupts
68 * cross-call interrupts, as mentioned, so we must go through a
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| /titanic_51/usr/src/uts/common/io/cxgbe/t4nex/ |
| H A D | t4_nexus.c | 120 int intr_fwd; /* Interrupts forwarded */
421 * calculating how many interrupts to attempt to allocate. in t4_devo_attach()
568 * Setup Interrupts. in t4_devo_attach()
588 /* Multiple interrupts. The first one is always error intr */ in t4_devo_attach()
600 * direct interrupts. in t4_devo_attach()
613 * interrupts. in t4_devo_attach()
630 * direct interrupts. in t4_devo_attach()
655 sc->intr_type == DDI_INTR_TYPE_MSIX ? "MSI-X interrupts" : in t4_devo_attach()
656 sc->intr_type == DDI_INTR_TYPE_MSI ? "MSI interrupts" : in t4_devo_attach()
666 sc->intr_type == DDI_INTR_TYPE_MSIX ? "MSI-X interrupts" in t4_devo_attach()
[all...] |
| /titanic_51/usr/src/uts/common/io/usb/hcd/ehci/ |
| H A D | ehci_polled.c | 154 /* Allow interrupts to continue */ in ehci_hcdi_polled_input_init()
189 /* Allow interrupts to continue */ in ehci_hcdi_polled_input_init()
466 /* Allow interrupts to continue */ in ehci_hcdi_polled_output_init()
496 /* Allow interrupts to continue */ in ehci_hcdi_polled_output_init()
1024 /* Disable all list processing and interrupts */ in ehci_polled_save_state()
1032 /* Save any unprocessed normal mode ehci interrupts */ in ehci_polled_save_state()
1139 /* The first enter keyboard entry enable interrupts and periodic list */ in ehci_polled_save_state()
1141 /* Enable USB and Frame list rollover interrupts */ in ehci_polled_save_state()
1327 /* Enable all required EHCI interrupts */ in ehci_polled_start_processing()
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| /titanic_51/usr/src/uts/sun4v/io/niumx/ |
| H A D | niumx.c | 220 /* check for pending interrupts, busy wait if so */ in niumx_intr_dist()
871 "interrupts", (caddr_t)&inos_p, &inoslen) in niumx_intr_ops()
1007 /* check for pending interrupts, busy wait if so */ in niumx_set_intr_target()
1040 * This function is called to register interrupts.
1130 * This function is called to unregister interrupts.
1156 /* check for pending interrupts, busy wait if so */ in niumx_rem_intr()
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| /titanic_51/usr/src/uts/common/dtrace/ |
| H A D | dcpc.c | 554 * synchronize processing of hardware overflow interrupts wth configuration
560 * overflow mechanism and interrupts may be processed). Before modifying
568 * the dcpc provider is no longer interested in overflow interrupts.
590 * overflow interrupts can be processed safely.
626 * the dcpc provider is no longer processing overflow interrupts. Only called
965 * order to stop overflow interrupts being processed in dcpc_cpu_setup()
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| /titanic_51/usr/src/uts/common/io/sata/adapters/ahci/ |
| H A D | ahci.c | 570 * Re-initialize the controller and enable the interrupts and in ahci_attach()
824 * Disable the whole controller interrupts before adding in ahci_attach()
854 "trying FIXED interrupts", NULL); in ahci_attach()
1052 /* disable the interrupts for an uninterrupted detach */ in ahci_detach()
1077 /* remove the interrupts */ in ahci_detach()
1105 * will not generate interrupts or modify or access memory. in ahci_detach()
1129 * Disable the interrupts and stop all the ports. in ahci_detach()
1528 * Either interrupts or polling could be used - it's up to the driver.
1540 * The command may be queued (callback function specified). Interrupts could
3148 /* Enable the interrupts o in ahci_tran_hotplug_port_activate()
[all...] |
| /titanic_51/usr/src/uts/sun4v/ml/ |
| H A D | trap_table.s | 64 * cases where you always want to process any pending interrupts before
795 * LEVEL_INTERRUPT is for level N interrupts.
2780 * Due to the design of UltraSPARC pipeline, pending interrupts are not
2783 * to execute first before taking any interrupts. If that instruction
2785 * entirely at TL=1 with interrupts disabled, then pending interrupts
2789 * A malicious user program can use this feature to block out interrupts
2793 * This problem is addressed by servicing any pending interrupts via
2796 * runs entirely at TL=1 with interrupts disabled, is replaced with the
2800 * We check for any pending interrupts her
[all...] |
| /titanic_51/usr/src/uts/common/os/ |
| H A D | ddi_intr_impl.c | 228 * Return the number of interrupts currently available.
262 * Return the limit of how many interrupts a driver can allocate.
374 * associated with a dev_info node. For devices with multiple interrupts per
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| /titanic_51/usr/src/uts/sun4u/montecarlo/sys/ |
| H A D | pcf8574_nct.h | 142 * This device is driven by interrupts. Each time it interrupts
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| /titanic_51/usr/src/uts/sun4u/montecarlo/io/ |
| H A D | se.conf | 32 interrupts=1
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| /titanic_51/usr/src/uts/common/io/ib/clients/rdsv3/ |
| H A D | rdsv3.conf | 28 # use echo '::interrupts -d' | mdb -k | grep hermon
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| /titanic_51/usr/src/uts/common/xen/public/ |
| H A D | xen.h | 141 * VIRTUAL INTERRUPTS
143 * Virtual interrupts that a guest OS may receive from Xen.
483 * 2. Physical interrupts. A domain with suitable hardware-access
486 * 3. Virtual interrupts ('events'). A domain can bind an event-channel
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| /titanic_51/usr/src/uts/common/io/xge/hal/include/ |
| H A D | xgehal-types.h | 332 * @XGE_HAL_BADCFG_BIMODAL_INTR: Invalid value to configure bimodal interrupts
559 /* MSI level Interrupts */
575 /* DMA level Interrupts */
578 /* PFC block interrupts */
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| /titanic_51/usr/src/grub/grub-0.97/netboot/ |
| H A D | natsemi.c | 469 /* Disable interrupts using the mask. */ in natsemi_reset()
721 * Description: Turns off interrupts and stops Tx and Rx engines
735 /* Disable interrupts using the mask. */ in natsemi_disable()
748 * Description: Enable, Disable, or Force interrupts
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| /titanic_51/usr/src/uts/common/io/1394/adapters/ |
| H A D | hci1394_attach.c | 197 * Turn on link, Reset Bus, enable interrupts. Should be the in hci1394_attach()
200 * interrupts. in hci1394_attach()
245 /* turn on the link, enable interrupts, reset the bus */ in hci1394_attach()
863 /* Don't allow the HW to generate any more interrupts */ in hci1394_cleanup()
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| H A D | hci1394_ixl_isr.c | 456 * interrupts allowed with no I/O completions in hci1394_ixl_intr_check_xfer()
463 * reinit remaining count of interrupts allowed in hci1394_ixl_intr_check_xfer()
470 * if no remaining count of interrupts allowed with no in hci1394_ixl_intr_check_xfer()
982 * interrupts, we will incorrectly restart the counting process. in hci1394_isoch_cycle_inconsistent()
1075 * interrupts, we will incorrectly restart the counting process. in hci1394_isoch_cycle_lost()
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| /titanic_51/usr/src/uts/sun4u/starcat/io/ |
| H A D | iosram.c | 324 * enable SBBC interrupts if SBBC is mapped in in iosram_attach()
335 * interrupts. in iosram_attach()
391 * Get interrupts cookies and initialize per-instance mutexes in iosram_attach()
493 * Disable SBBC interrupts if SBBC is mapped in in iosram_detach()
1394 * no interrupts are pending. in iosram_softintr()
1433 * interrupts. Instead, we trigger a soft interrupt when the driver in iosram_softintr()
2015 * Map the target IOSRAM, read the TOC, and register interrupts if not in iosram_switch_tunnel()
2115 * Also unmap old master IOSRAM and remove any interrupts in iosram_switch_tunnel()
2148 * Since incoming interrupts could get lost during a tunnel switch, in iosram_switch_tunnel()
2150 * of wasted effort will be caused if no interrupts wer in iosram_switch_tunnel()
[all...] |
| /titanic_51/usr/src/man/man1m/ |
| H A D | intrd.1m | 19 between interrupts and \fBCPU\fRs. If \fBintrd\fR decides that the current
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| /titanic_51/usr/src/man/man7d/ |
| H A D | npe.7d | 19 PCI Express error handling and PCI Express MSI interrupts.
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| /titanic_51/usr/src/uts/common/io/nge/ |
| H A D | nge.conf | 33 # level interrupts
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| /titanic_51/usr/src/uts/common/io/mac/ |
| H A D | mac_util.c | 570 * re-targeting for legacy (fixed) interrupts. Some older versions
571 * of the popular NICs like e1000g do not support MSI-X interrupts
572 * and they reserve fixed interrupts for RX/TX rings. To re-target
573 * these interrupts, PCITOOL ioctls need to be used.
695 * Get the interrupts and check each one to see if it is for our device.
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| /titanic_51/usr/src/uts/common/io/ |
| H A D | pci_intr_lib.c | 670 * For a given type (MSI/X) returns the number of interrupts supported
704 * For a given type (MSI/X) sets the number of interrupts supported
941 * It is only called if no more MSI-X interrupts are being used.
1033 /* Disable the interrupts */ in pci_intx_get_cap()
1089 /* Enable the interrupts */ in pci_intx_clr_mask()
1121 /* Disable the interrupts */ in pci_intx_set_mask()
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| /titanic_51/usr/src/uts/common/io/bnxe/577xx/drivers/common/include/vm/ |
| H A D | vfpf_if.h | 197 u16 hc_rate; /* desired interrupts per sec. */
228 u16 hc_rate; /* desired interrupts per sec. */
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| /titanic_51/usr/src/uts/sparc/sys/ |
| H A D | spl.h | 44 * XXX - This is a hack for softcall to block all i/o interrupts.
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| /titanic_51/usr/src/uts/sfmmu/ml/ |
| H A D | sfmmu_asm.s | 531 .asciz "sfmmu_asm: interrupts already disabled"
547 .asciz "sfmmu_asm: interrupts not disabled"
590 * The caller must disable interrupts before entering this routine.
1469 wrpr %o5, PSTATE_IE, %pstate /* disable interrupts */
1474 wrpr %g0, %o5, %pstate /* enable interrupts */
1509 wrpr %o5, PSTATE_IE, %pstate ! disable interrupts
1528 wrpr %g0, %o5, %pstate ! enable interrupts
3899 * disable interrupts
3906 * disable interrupts to protect the TSBMISS area
4003 wrpr %g0, %o3, %pstate /* re-enable interrupts */
[all...] |