| /titanic_53/usr/src/uts/common/sys/usb/hcd/openhci/ |
| H A D | ohcid.h | 57 * information that includes interrupts for which ohci interrupt handler
59 * will be used later in normal mode to service those missed interrupts.
61 * and WriteDoneHead interrupts because of this polled switch.
79 uint_t ohci_curr_intr_sts; /* Current interrupts */
87 uint_t ohci_critical_intr_sts; /* Critical interrupts */
93 * pending when polled code is entered. These missed interrupts &
98 uint_t ohci_missed_intr_sts; /* Missed interrupts */
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| /titanic_53/usr/src/uts/intel/io/acpica/ |
| H A D | acpi_enum.c | 136 resource_ptr->Data.Irq.Interrupts[i]; in parse_resources_irq()
137 used_interrupts |= 1 << resource_ptr->Data.Irq.Interrupts[i]; in parse_resources_irq()
141 i, resource_ptr->Data.Irq.Interrupts[i]); in parse_resources_irq()
558 * on LX50, you get interrupts of mouse and keyboard in parse_resources()
583 "interrupts", (int *)interrupt, interrupt_count); in parse_resources()
617 "interrupts", (int *)i8042_intrs, 2); in get_bus_dip()
999 "interrupts", (int *)intr, count); in used_res_interrupts()
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| /titanic_53/usr/src/uts/sun4u/io/pci/ |
| H A D | pci_intr.c | 217 * pci_unclaimed_intr_max within the time limit, then all interrupts
274 * There is a count of unclaimed interrupts kept on a per-ino basis. If at
280 * interrupts on that ino. The state machine will only be idled again if a
459 ib_ino_info_t *ino_p; /* pulse interrupts have no ino */ in pci_add_intr()
594 atomic_inc_32_nv(&pciintr_ks_instance), "config", "interrupts", in pci_add_intr()
723 * interrupts are torn down by their respective block destroy routines:
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| H A D | pcisch.c | 131 * The initialization of cb internal interrupts depends on ib in pci_obj_setup()
261 "interrupts", (caddr_t)&intr_buf, &intr_len) != DDI_SUCCESS) in pci_intr_setup()
262 cmn_err(CE_PANIC, "%s%d: no interrupts property\n", in pci_intr_setup()
267 cmn_err(CE_PANIC, "%s%d: <%d interrupts", ddi_driver_name(dip), in pci_intr_setup()
281 if (ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "interrupts", in pci_intr_setup()
283 cmn_err(CE_PANIC, "%s%d: cannot update interrupts property\n", in pci_intr_setup()
581 * Schizo maps all interrupts in one contiguous area. in ib_intr_map_reg_addr()
608 * return true if there are interrupts using this mapping register
750 * Enable error interrupts. in pbm_configure()
758 * Enable pci streaming byte errors and error interrupts. in pbm_configure()
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| /titanic_53/usr/src/uts/i86xpv/io/psm/ |
| H A D | xpv_uppc.c | 370 * interrupts should be generated. There is no need to support the periodic
406 * This function will enable timer interrupts.
415 * This function will disable timer interrupts on the current cpu.
801 * It is called with interrupts disabled, and does not enable interrupts.
830 * If new ipl level will enable any pending interrupts, setup so the in xen_uppc_setspl()
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| /titanic_53/usr/src/uts/common/io/hxge/ |
| H A D | hxge_hw.c | 160 * logical device interrupts us and then call in hxge_intr()
183 "no interrupts on group %d", t_ldgp->ldg)); in hxge_intr()
211 * Re-arm group interrupts in hxge_intr()
239 * continued interrupts. in hxge_peu_handle_sys_errors()
372 * This interrupt handler is for system error interrupts. in hxge_syserr_intr()
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| /titanic_53/usr/src/uts/common/io/sata/adapters/si3124/ |
| H A D | si3124.c | 617 * Disable all the interrupts before adding interrupt in si_attach()
618 * handler(s). The interrupts shall be re-enabled selectively in si_attach()
651 "will try Legacy interrupts", NULL); in si_attach()
659 * fixed interrupts are available on the system. in si_attach()
678 "si3124: No interrupts registered", NULL); in si_attach()
818 /* disable the interrupts for an uninterrupted detach */ in si_detach()
843 /* remove the interrupts */ in si_detach()
1924 /* disable the interrupts on the port. */ in si_tran_hotplug_port_deactivate()
2329 * interrupts enabled or disabled.
2388 * Interrupts and timers may not be working properly in a crash dump in si_poll_cmd()
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| /titanic_53/usr/src/uts/sun4u/os/ |
| H A D | mach_startup.c | 285 * Disable interrupts now, so that we'll awaken immediately in cpu_halt()
289 * We check for the presence of our bit after disabling interrupts. in cpu_halt()
298 * cpu_halt() must disable interrupts, then check for the bit. in cpu_halt()
306 * will filter spurious interrupts that wake us up, but don't in cpu_halt()
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| /titanic_53/usr/src/man/man1m/ |
| H A D | intrstat.1m | 22 table contains both the raw number of interrupts for the given device on the
48 raise interrupts while the command is running. Any devices that are silent
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| H A D | mpstat.1m | 87 interrupts
96 interrupts as threads (not counting clock interrupt)
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| /titanic_53/usr/src/uts/sun/io/audio/drv/audiocs/ |
| H A D | audio_4231_apcdma.c | 120 /* clear the CSR so we have all interrupts disabled */ in apc_map_regs()
152 * with interrupts and the DMA engine disabled.
238 * Start the DMA engine, including interrupts. in apc_start_engine()
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| /titanic_53/usr/src/uts/intel/io/acpica/hardware/ |
| H A D | hwsleep.c | 62 * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED
219 * Called with interrupts ENABLED.
288 * Called with interrupts ENABLED.
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| /titanic_53/usr/src/uts/sun4u/starcat/sys/ |
| H A D | iosramvar.h | 94 * Interrupt priority (PIL) used for IOSRAM interrupts. The value 5 was
267 uint32_t intr_recv; /* # interrupts received */
269 uint32_t intr_send; /* # interrupts sent */
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| /titanic_53/usr/src/uts/common/io/sata/adapters/nv_sata/ |
| H A D | nv_sata.c | 327 * Maximum number of consecutive interrupts processed in the loop in the
711 "will try Legacy interrupts"); in nv_attach()
718 * the fixed interrupts are available on the system. in nv_attach()
742 "no interrupts registered", NULL); in nv_attach()
918 * Remove interrupts in nv_detach()
1532 * interrupts and sleep wait on a cv.
1535 * interrupts and must busy wait and simulate the
1536 * interrupts by waiting for BSY to be cleared.
2003 * disable the interrupts on port in nv_sata_deactivate()
2522 * clear any previous interrupts asserted in mcp5x_reg_init()
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| /titanic_53/usr/src/uts/i86pc/os/ |
| H A D | ddi_impl.c | 462 * determine if the driver is expecting the new style "interrupts" in impl_xlate_intrs()
468 * "interrupts" property. in impl_xlate_intrs()
473 /* the old style "interrupts" property... */ in impl_xlate_intrs()
510 /* the new style "interrupts" property... */ in impl_xlate_intrs()
585 * The "reg" and either an "intr" or "interrupts" properties are required
586 * if the driver wishes to create mappings or field interrupts on behalf
597 * The "interrupts" property is assumed to be a list of at least one
641 * Handle the 'intr' and 'interrupts' properties in make_ddi_ppd()
655 * we need to support the generalized 'interrupts' property. in make_ddi_ppd()
657 if (get_prop_int_array(child, "interrupts", &irupts_prop, in make_ddi_ppd()
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| /titanic_53/usr/src/uts/common/io/bnxe/ |
| H A D | bnxe_binding.h | 135 * PRV_CTL_DISABLE_INTR - disable interrupts, no data passed
136 * PRV_CTL_ENABLE_INTR - enable interrupts, no data passed
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| /titanic_53/usr/src/uts/sun4u/serengeti/sys/ |
| H A D | sgsbbc_priv.h | 62 * Different interrupts
172 * SBBC Interrupts
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| /titanic_53/usr/src/uts/sun4v/io/ |
| H A D | vnet_dds.c | 875 int interrupts[VDDS_MAX_VRINTRS]; in vdds_new_niu_node() local
1016 rv = vdds_get_interrupts(cba->cookie, rnum, interrupts, &nintr); in vdds_new_niu_node()
1018 DERR(NULL, "Failed to get interrupts for cookie=0x%lx", in vdds_new_niu_node()
1023 /* create "interrupts" property */ in vdds_new_niu_node()
1024 if (ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "interrupts", in vdds_new_niu_node()
1025 interrupts, nintr) != DDI_SUCCESS) { in vdds_new_niu_node()
1026 DERR(NULL, "Failed to update interrupts property(dip=0x%p)", in vdds_new_niu_node()
1107 * then provides them to create interrupts property.
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| /titanic_53/usr/src/uts/common/io/usb/hcd/ehci/ |
| H A D | ehci_util.c | 711 * Register interrupts and initialize each mutex and condition variables
834 * Register FIXED or MSI interrupts.
846 /* Get number of interrupts */ in ehci_add_intrs()
856 /* Get number of available interrupts */ in ehci_add_intrs()
976 /* Enable all interrupts */ in ehci_add_intrs()
978 /* Call ddi_intr_block_enable() for MSI interrupts */ in ehci_add_intrs()
982 /* Call ddi_intr_enable for MSI or FIXED interrupts */ in ehci_add_intrs()
1115 * interrupts unless the Root hub ports are routed to the EHCI in ehci_init_workaround()
1117 * the presence of SOFs interrupts. in ehci_init_workaround()
1210 "No SOF interrupts have been received, this USB EHCI host" in ehci_init_check_status()
[all …]
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| /titanic_53/usr/src/uts/i86pc/io/amd_iommu/ |
| H A D | amd_iommu_impl.c | 555 /* No interrupts for completion wait - too heavy weight. use polling */ in amd_iommu_enable_interrupts()
690 "MSI interrupts not supported. Failing init.", in amd_iommu_setup_interrupts()
710 "MSI number of interrupts requested: %d", in amd_iommu_setup_interrupts()
716 "interrupts requested. Failing init", f, in amd_iommu_setup_interrupts()
731 "MSI number of interrupts available: %d", in amd_iommu_setup_interrupts()
737 "interrupts available. Failing init", f, in amd_iommu_setup_interrupts()
744 "interrupts: requested (%d) > available (%d). " in amd_iommu_setup_interrupts()
766 "MSI power of 2 number of interrupts: %d,%d", in amd_iommu_setup_interrupts()
785 "number of interrupts actually allocated %d", in amd_iommu_setup_interrupts()
823 "interrupts: intrcap0 (%d) < intrcapN (%d)", in amd_iommu_setup_interrupts()
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| /titanic_53/usr/src/cmd/mdb/sparc/modules/intr/ |
| H A D | intr.c | 554 if (mdb_walk_dcmd("interrupts", "interrupts", argc, argv) in intr_intr()
570 { "interrupts", "[-d]", "display the interrupt info registered with "
576 { "interrupts", "walk PCI/PX interrupt structures",
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| /titanic_53/usr/src/uts/i86pc/io/ioat/ |
| H A D | ioat.c | 242 /* Enable device interrupts */ in ioat_attach()
591 /* Clear any pending interrupts */ in ioat_intr_enable()
600 /* Enable interrupts on the device */ in ioat_intr_enable()
613 * disable interrupts on the device. A read of the interrupt control in ioat_intr_disable()
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| /titanic_53/usr/src/uts/common/os/ |
| H A D | panic.c | 76 * all other CPUs are stopped and low-level interrupts have been blocked.
248 * We want to indicate that high-level interrupts are in panicsys()
278 * We currently have all interrupts blocked, and expect that in panicsys()
308 * keyboard interrupts to enter the debugger. These callbacks in panicsys()
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| /titanic_53/usr/src/uts/common/sys/ |
| H A D | pcmcia.h | 123 * shared interrupts are handled by the
242 #define PCA_IRQ_SHAREABLE 0x0020 /* all interrupts sharable */
243 #define PCA_IRQ_ISA 0x0040 /* ISA style (host) interrupts */
494 #define PCMCIA_PROP_INTR 8 /* interrupts property */
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| /titanic_53/usr/src/uts/sun4u/opl/io/pcicmu/ |
| H A D | pcicmu.c | 104 * The following value is the number of consecutive unclaimed interrupts that
988 /* PCI nexus driver supports only fixed interrupts */ in pcmu_intr_ops()
1103 * Get the interrupts property. in pcmu_intr_setup()
1106 "interrupts", (caddr_t)&pcmu_p->pcmu_inos, in pcmu_intr_setup()
1108 cmn_err(CE_PANIC, "%s%d: no interrupts property\n", in pcmu_intr_setup()
1113 * figure out number of interrupts in the "interrupts" property in pcmu_intr_setup()
1305 * interrupts.
1498 * Disable error and streaming byte hole interrupts via the in pcmu_pbm_disable_errors()
1504 * Disable error interrupts via the interrupt mapping register. in pcmu_pbm_disable_errors()
1611 {"pio_cycles_b", 0xf}, {"interrupts", 0x11},
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