| /titanic_53/usr/src/psm/promif/ieee1275/sun4/ |
| H A D | prom_set_traptable.c | 35 * interrupts and handle any pending soft interrupts.
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| /titanic_53/usr/src/uts/common/io/fibre-channel/fca/oce/ |
| H A D | oce_intr.c | 35 * top level function to setup interrupts
229 * function to enable interrupts
268 * function to disable interrupts
288 "Failed to disable interrupts 0x%x", ret); in oce_di()
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| /titanic_53/usr/src/uts/sun4/io/ |
| H A D | ivintr.c | 74 * used for hardware and software interrupts. in init_ivintr()
109 * and single or multi target software interrupts either from the reserved
141 "target software interrupts, %d", MAX_RSVD_IVX); in iv_alloc()
147 * interrupts. Create a kmem cache for the interrupt allocation, in iv_alloc()
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| /titanic_53/usr/src/uts/common/sys/ |
| H A D | ddi_intr.h | 136 * *nintrsp*, the number of interrupts the device supports for the
145 * *navailp*, the number of interrupts currently available for the
237 * Return DDI_FAILURE if the device has no interrupts.
311 * Like ddi_add_intr, only for system interrupts that you can trigger
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| /titanic_53/usr/src/man/man1m/ |
| H A D | psradm.1m | 36 disable interrupts for an \fBoff-line\fR processor. Thus, the actual effect of
68 interrupts.
308 system that can service interrupts needed by the system.
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| /titanic_53/usr/src/uts/i86pc/os/ |
| H A D | cpr_impl.c | 133 * Set machine up to take interrupts
223 * Enable interrupts on this cpu. in i_cpr_save_context()
224 * Do not bind interrupts to this CPU's local APIC until in i_cpr_save_context()
225 * the CPU is ready to receive interrupts. in i_cpr_save_context()
244 * Disable interrupts on this CPU so that PSM knows not to bind in i_cpr_save_context()
245 * interrupts here on resume until the CPU has executed in i_cpr_save_context()
709 * Enable interrupts on boot cpu. in i_cpr_power_down()
894 * Clear the IDT as interrupts will be off and a limit of 0 will cause in init_real_mode_platter()
945 * this with interrupts disabled. in i_cpr_start_cpu()
987 (void) spl0(); /* enable interrupts */ in i_cpr_start_cpu()
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| /titanic_53/usr/src/uts/common/os/ |
| H A D | cpu_event.c | 195 * The target CPU disables interrupts before clearing corresponding bit and
664 * interrupts enabled or disabled, so we need to make sure interrupts in cpu_idle_enter()
694 * cpu_idle_enter runs with interrupts in cpu_idle_enter()
696 * also be called with interrupts disabled. in cpu_idle_enter()
698 * enable the interrupts, if they can also in cpu_idle_enter()
768 * handler. When called from interrupt handler, interrupts will be in cpu_idle_exit()
769 * disabled. When called from idle thread, interrupts may be disabled in cpu_idle_exit()
773 /* Called from interrupt, interrupts are already disabled. */ in cpu_idle_exit()
1153 * Now target CPU is spinning in a pause loop with interrupts disabled. in cpu_idle_intercept_cpu()
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| /titanic_53/usr/src/psm/promif/ieee1275/sun4v/ |
| H A D | prom_set_mmfsa_traptable.c | 35 * interrupts and handle any pending soft interrupts.
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| /titanic_53/usr/src/man/man7d/ |
| H A D | uhci.7d | 116 \fBNo SOF interrupts have been received. This USB UHCI host controller is
121 The USB hardware is not generating Start Of Frame interrupts. Please reboot the
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| H A D | ohci.7d | 130 \fBNo SOF interrupts have been received. This OHCI USB controller is
135 The USB hardware is not generating Start Of Frame interrupts. Please reboot the
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| /titanic_53/usr/src/man/man9f/ |
| H A D | ddi_intr_get_pending.9f | 50 interrupt pending bits of its interrupts. The driver should use
52 flag is returned to indicate that interrupts support interrupt pending bits.
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| /titanic_53/usr/src/uts/sun4v/vm/ |
| H A D | mach_sfmmu_asm.s | 230 * From resume we call sfmmu_setctx_sec with interrupts disabled.
231 * But we can also get called from C with interrupts enabled. So,
235 /* If interrupts are not disabled, then disable them */
239 wrpr %g1, PSTATE_IE, %pstate /* disable interrupts */
251 wrpr %g0, %g1, %pstate /* enable interrupts */
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| /titanic_53/usr/src/uts/i86xpv/io/psm/ |
| H A D | mp_platform_xpv.c | 140 * for those interrupts (like MSI/X) that don't have a physical IRQ.
311 * Both add and delspl are complicated by the fact that different interrupts
314 * 1a. with interrupts at different IPLs
315 * 1b. with interrupts at same IPL
484 * If there are more interrupts at a higher IPL, we don't need in apic_delspl_common()
622 * If there are still active interrupts, we are done. in apic_delspl_common()
1155 /* setup I/O APIC entry for non-MSI/X interrupts */ in apic_setup_irq_table()
1298 * Mark vector as being in the process of being deleted. Interrupts
1301 * addspl and delspl with interrupts disabled. Because an interrupt
1404 * Must be called with interrupts disabled and apic_ioapic_lock held
[all …]
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| /titanic_53/usr/src/uts/i86pc/io/ |
| H A D | mp_platform_misc.c | 152 * for those interrupts (like MSI/X) that don't have a physical IRQ.
355 * Both add and delspl are complicated by the fact that different interrupts
358 * 1a. with interrupts at different IPLs
359 * 1b. with interrupts at same IPL
528 * If there are more interrupts at a higher IPL, we don't need in apic_delspl_common()
666 * If there are still active interrupts, we are done. in apic_delspl_common()
1201 /* setup I/O APIC entry for non-MSI/X interrupts */ in apic_setup_irq_table()
1344 * Mark vector as being in the process of being deleted. Interrupts
1347 * addspl and delspl with interrupts disabled. Because an interrupt
1450 * Must be called with interrupts disabled and apic_ioapic_lock held
[all …]
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| /titanic_53/usr/src/uts/i86pc/io/pcplusmp/ |
| H A D | apic_timer.c | 352 * interrupts should be generated. There is no need to support the periodic
366 * This function will enable timer interrupts.
379 * This function will disable timer interrupts.
402 * Should be called with interrupts disabled. in apic_timer_stop_count()
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| /titanic_53/usr/src/cmd/cmd-inet/usr.sbin/snoop/ |
| H A D | snoop_rstat.c | 151 (void) showxdr_u_long("Interrupts = %lu"); in detail_stats()
180 (void) showxdr_u_long("Interrupts = %lu"); in detail_statsswtch()
216 (void) showxdr_u_long("Interrupts = %lu"); in detail_statstime()
257 (void) showxdr_u_long("Interrupts = %lu"); in detail_statsvar()
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| /titanic_53/usr/src/uts/i86pc/sys/ |
| H A D | hpet_acpi.h | 39 * Solaris uses an HPET Timer to generate interrupts for CPUs in Deep C-state
46 * Please see the Intel Programmer's guides. Interrupts are disabled before
48 * before servicing interrupts.) When a Deep C-state CPU wakes up (due to
50 * The CPU returning from Deep C-state must enable interrupts before it will
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| /titanic_53/usr/src/uts/common/io/rge/ |
| H A D | rge_main.c | 737 * Start chip processing, including enabling interrupts in rge_start()
1295 * Register FIXED or MSI interrupts.
1308 /* Get number of interrupts */ in rge_add_intrs()
1316 /* Get number of available interrupts */ in rge_add_intrs()
1402 * Unregister FIXED or MSI interrupts
1409 /* Disable all interrupts */ in rge_rem_intrs()
1577 * we don't support high level interrupts in the driver in rge_attach()
1623 * accesses, but with interrupts and Bus Mastering off. in rge_attach()
1627 * and allow interrupts only when everything else is set up. in rge_attach()
1700 * interrupts ... in rge_attach()
[all …]
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| /titanic_53/usr/src/uts/sun4u/opl/sys/pcicmu/ |
| H A D | pcmu_ib.h | 46 uint_t ih_intr_state; /* Only used for fixed interrupts */
70 volatile uint_t pino_unclaimed; /* number of unclaimed interrupts */
99 * Only used for fixed or legacy interrupts
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| /titanic_53/usr/src/uts/sun4u/io/px/ |
| H A D | px_err_impl.h | 56 * *intr_mask_p bitmask for enabled interrupts
57 * *log_mask_p bitmask for logged interrupts
58 * *count_mask_p bitmask for counted interrupts
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| /titanic_53/usr/src/man/man4/ |
| H A D | cardbus.4 | 113 \fB\fBinterrupts\fR\fR
132 Only devices that generate interrupts support an \fBinterrupts\fR property.
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| /titanic_53/usr/src/man/man1/ |
| H A D | trap.1 | 55 \fBonintr\fR controls the action of the shell on interrupts. With no arguments,
56 \fBonintr\fR restores the default action of the shell on interrupts. (The shell
58 the \fB\(mi\fR argument, the shell ignores all interrupts. With a \fIlabel\fR
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| /titanic_53/usr/src/uts/i86pc/io/pci/ |
| H A D | pci_kstats.c | 98 * added, not enabled. There may be a period where interrupts are not in pci_ih_ks_update()
164 _MODULE_NAME, "interrupts", KSTAT_TYPE_NAMED, in pci_kstat_create()
187 * interrupts.
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| /titanic_53/usr/src/uts/sun4/io/px/ |
| H A D | px_ib.c | 192 * the interrupts properly. in px_ib_intr_pend()
223 /* Skip enabling disabled interrupts */ in px_ib_intr_dist_en()
241 /* Wait on pending interrupts */ in px_ib_intr_dist_en()
283 * Redistribute interrupts of the specified weight. The first call has a weight
303 /* Redistribute internal interrupts */ in px_ib_intr_redist()
313 /* Redistribute device interrupts */ in px_ib_intr_redist()
341 * As part of redistributing weighted interrupts over cpus, in px_ib_intr_redist()
342 * nexus redistributes device interrupts and updates in px_ib_intr_redist()
422 * Reset interrupts to IDLE. This function is called during
423 * panic handling after redistributing interrupts; it's needed to
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| /titanic_53/usr/src/uts/sun4u/io/ |
| H A D | opl_cfg.c | 2039 * interrupts may be received from PCI devices. These interrupts
2041 * interrupts need to be cleared on the CPU side so that the CPU may
2043 * interrupts are expected to reraise the interrupts after sometime
2045 * chance to properly service the interrupts.
2060 * Note that the only handling done for interrupts here is to clear it
2069 * control from OBP when interrupts happen at a port after L1A, etc.
2092 * interrupts that need to be handled for a CMU channel:
2093 * - obio interrupts
2094 * - pci interrupts
2155 * task is to simply reset received interrupts on the CPU side.
[all …]
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