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/titanic_44/usr/src/uts/common/io/rge/
H A Drge_main.c737 * Start chip processing, including enabling interrupts in rge_start()
1295 * Register FIXED or MSI interrupts.
1308 /* Get number of interrupts */ in rge_add_intrs()
1316 /* Get number of available interrupts */ in rge_add_intrs()
1402 * Unregister FIXED or MSI interrupts
1409 /* Disable all interrupts */ in rge_rem_intrs()
1577 * we don't support high level interrupts in the driver in rge_attach()
1623 * accesses, but with interrupts and Bus Mastering off. in rge_attach()
1627 * and allow interrupts only when everything else is set up. in rge_attach()
1700 * interrupts ... in rge_attach()
[all …]
/titanic_44/usr/src/man/man1/
H A Dkvmstat.129 injected interrupts, emulations, and more, on a per virtual CPU basis.
84 Count of interrupts injected into the virtual CPU over
H A Dw.1142 highest numbered process on the terminal that is not ignoring interrupts, or,
146 interrupts. In cases where no process can be found, \fBw\fR prints
/titanic_44/usr/src/uts/sun4/io/px/
H A Dpx_ib.c192 * the interrupts properly. in px_ib_intr_pend()
223 /* Skip enabling disabled interrupts */ in px_ib_intr_dist_en()
241 /* Wait on pending interrupts */ in px_ib_intr_dist_en()
283 * Redistribute interrupts of the specified weight. The first call has a weight
303 /* Redistribute internal interrupts */ in px_ib_intr_redist()
313 /* Redistribute device interrupts */ in px_ib_intr_redist()
341 * As part of redistributing weighted interrupts over cpus, in px_ib_intr_redist()
342 * nexus redistributes device interrupts and updates in px_ib_intr_redist()
422 * Reset interrupts to IDLE. This function is called during
423 * panic handling after redistributing interrupts; it's needed to
H A Dpx_intr.c67 * pci_unclaimed_intr_max within the time limit, then all interrupts
131 * There is a count of unclaimed interrupts kept on a per-ino basis. If at
137 * interrupts on that ino. The state machine will only be idled again if a
233 * There is a count of unclaimed interrupts kept on a per-ino basis. If at
239 * interrupts on that ino. The state machine will only be idled again if a
271 * lower priority interrupts will just process any unprocessed MSIQ in px_msiq_intr()
921 "interrupts", KSTAT_TYPE_NAMED, in px_create_intr_kstats()
938 * interrupt pins interrupts.
1093 * interrupt pins interrupts.
1151 * This function is called to register MSI/Xs and PCIe message interrupts.
[all …]
/titanic_44/usr/src/uts/sun4u/io/
H A Dopl_cfg.c2039 * interrupts may be received from PCI devices. These interrupts
2041 * interrupts need to be cleared on the CPU side so that the CPU may
2043 * interrupts are expected to reraise the interrupts after sometime
2045 * chance to properly service the interrupts.
2060 * Note that the only handling done for interrupts here is to clear it
2069 * control from OBP when interrupts happen at a port after L1A, etc.
2092 * interrupts that need to be handled for a CMU channel:
2093 * - obio interrupts
2094 * - pci interrupts
2155 * task is to simply reset received interrupts on the CPU side.
[all …]
H A Dzuluvm.c1333 if (zdev->interrupts[i].ino != -1) { in zuluvm_do_retarget()
1335 idx = zdev->interrupts[i].offset; in zuluvm_do_retarget()
1385 zdev->imr[zdev->interrupts[ino].offset] &= ~ZULUVM_IMR_V_MASK; in zuluvm_rem_intr()
1461 zdev->interrupts[i].offset = 0; in zuluvm_get_intr_props()
1462 zdev->interrupts[i].ino = -1; in zuluvm_get_intr_props()
1466 "interrupts", &intr, &nintr) == DDI_PROP_SUCCESS) { in zuluvm_get_intr_props()
1469 cmn_err(CE_WARN, "%s%d: no interrupts in property", in zuluvm_get_intr_props()
1476 cmn_err(CE_WARN, "%s%d: to many interrupts (%d)", in zuluvm_get_intr_props()
1483 zdev->interrupts[i].offset = intr[i]; in zuluvm_get_intr_props()
1484 zdev->interrupts[i].ino = i; in zuluvm_get_intr_props()
[all …]
/titanic_44/usr/src/uts/sun4v/os/
H A Dmach_startup.c165 * Disable interrupts now, so that we'll awaken immediately in cpu_halt()
169 * We check for the presence of our bit after disabling interrupts. in cpu_halt()
178 * cpu_halt() must disable interrupts, then check for the bit. in cpu_halt()
186 * will filter spurious interrupts that wake us up, but don't in cpu_halt()
321 * one strand can't handle interrupts for a 1Gb NIC. So set the tunable
/titanic_44/usr/src/uts/common/io/nxge/
H A Dnxge_txc.c68 /* Unmask all TXC interrupts */ in nxge_txc_init()
167 /* Mask all TXC interrupts for <port>. */ in nxge_txc_tdc_bind()
210 /* Unmask all TXC interrupts on <port> */ in nxge_txc_tdc_bind()
264 /* Mask all TXC interrupts for <port>. */ in nxge_txc_tdc_unbind()
282 /* Unmask all TXC interrupts on <port> */ in nxge_txc_tdc_unbind()
/titanic_44/usr/src/man/man9e/
H A Dquiesce.9e41 generates interrupts, modifies or accesses memory. The driver should reset the
59 longer has access to memory or interrupts.
/titanic_44/usr/src/man/man9f/
H A Dldi_prop_exists.9f160 /* Determine the existence of the "interrupts" property */
161 ldi_prop_exists(lh, LDI_DEV_T_ANY|DDI_PROP_NOTPROM, "interrupts");
/titanic_44/usr/src/uts/sun/sys/
H A Davintr.h53 * maximum number of autovectored interrupts at a given priority
85 * Fast interrupts go directly out of the
/titanic_44/usr/src/uts/common/io/bfe/
H A Dbfe_hw.h258 #define BFE_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */
259 #define BFE_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */
260 #define BFE_INTVEC_ILINE20 0x00000004 /* Enable interrupts for iline20 */
261 #define BFE_INTVEC_CODEC 0x00000008 /* Enable interrupts for v90 codec */
262 #define BFE_INTVEC_USB 0x00000010 /* Enable interrupts for usb */
264 #define BFE_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */
/titanic_44/usr/src/uts/sun4u/sys/
H A Dtodmostek.h45 * our TOD clock. Clock interrupts are generated by a separate timer
59 volatile uchar_t clk_interrupts; /* interrupts register */
/titanic_44/usr/src/man/man1m/
H A Dnfsstat.1m342 \fB\fBinterrupts\fR\fR
448 Interrupts allowed on hard mount.
478 No interrupts allowed on hard mount.
/titanic_44/usr/src/man/man4/
H A Dpci.4119 \fB\fBinterrupts\fR\fR
138 Only devices that generate interrupts support an \fBinterrupts\fR property.
/titanic_44/usr/src/uts/intel/io/acpica/hardware/
H A Dhwxfsleep.c193 * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED in ACPI_EXPORT_SYMBOL()
327 * This function must execute with interrupts enabled.
413 * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED in ACPI_EXPORT_SYMBOL()
451 * sleep. Called with interrupts DISABLED. in ACPI_EXPORT_SYMBOL()
483 * Called with interrupts ENABLED. in ACPI_EXPORT_SYMBOL()
/titanic_44/usr/src/uts/i86pc/os/cpupm/
H A Dcpu_idle.c279 * Toggle interrupt flag to detect pending interrupts. in acpi_cpu_mwait_check_wakeup()
303 * Toggle interrupt flag to detect pending interrupts. in acpi_cpu_mwait_ipi_check_wakeup()
319 * Toggle interrupt flag to detect pending interrupts. in acpi_cpu_check_wakeup()
415 * Disable interrupts here so we will awaken immediately after halting in acpi_cpu_cstate()
423 * We check for the presence of our bit after disabling interrupts. in acpi_cpu_cstate()
432 * acpi_cpu_cstate() must disable interrupts, then check for the bit. in acpi_cpu_cstate()
535 * Reprogram this CPU's LAPIC here before enabling interrupts. in acpi_cpu_cstate()
/titanic_44/usr/src/uts/sun4u/lw2plus/io/
H A Dlombus.c440 * side-effects, such as disabling interrupts), for such a in sio_put_reg()
443 * routine and re-enabling interrupts. This effect was in sio_put_reg()
444 * observed to lead to spurious (unclaimed) interrupts in in sio_put_reg()
553 * To investigate whether we're getting any abnormal interrupts
555 * chip-level interrupts are supposed to be enabled at this time.
567 * Enable/disable interrupts
598 * with mutex_init()), and whether chip interrupts are enabled.
612 * event, we would notice that chip interrupts haven't yet been
807 * Cyclic handler: just calls the receive routine, in case interrupts
908 * sure that SIO interrupts are enabled so we'll see the reply in lombus_cmd()
[all …]
/titanic_44/usr/src/uts/common/io/xge/hal/xgehal/
H A Dxgehal-device.c601 * @flag: if true - enable, otherwise - disable interrupts.
603 * Disable or enable device interrupts. Mask is used to specify
604 * which hardware blocks should produce interrupts. For details
618 /* PIC Interrupts */ in __hal_device_intr_mgmt()
659 * Mask both Link Up and Down interrupts in __hal_device_intr_mgmt()
682 /* DMA Interrupts */ in __hal_device_intr_mgmt()
683 /* Enabling/Disabling Tx DMA interrupts */ in __hal_device_intr_mgmt()
689 /* Enable all TxDMA interrupts */ in __hal_device_intr_mgmt()
722 /* Enabling/Disabling Rx DMA interrupts */ in __hal_device_intr_mgmt()
729 /* All RxDMA block interrupts are disabled for now in __hal_device_intr_mgmt()
[all …]
/titanic_44/usr/src/uts/common/io/i40e/
H A Di40e_sw.h132 * value will allow a certain number of interrupts per second.
134 * Our default values for RX allow 20k interrupts per second while our default
135 * values for TX allow for 5k interrupts per second. For other class interrupts,
274 * driver sees fit. But until we support more interrupts this seems
335 I40E_ATTACH_ALLOC_INTR = 0x0008, /* Interrupts allocated */
342 I40E_ATTACH_ENABLE_INTR = 0x1000, /* DDI interrupts enabled */
360 * I40E_INTR_ADJUST: Our interrupts are being manipulated and therefore we
/titanic_44/usr/src/uts/common/io/tpm/
H A Dtpm_tis.h43 /* Enable Interrupts */
49 /* Supported Interrupts */
/titanic_44/usr/src/uts/sun4/ml/
H A Dinterrupt.s354 * %pstate = normal globals, interrupts enabled,
783 ! If the thread being restarted isn't pinning anyone, and no interrupts
908 * %pstate = normal globals, interrupts enabled,
1129 ! Handle high-level interrupts on separate interrupt stack.
1130 ! No other high-level interrupts are active, so switch to int stack.
1159 wrpr %g0, %o2, %pil ! enable interrupts
1174 wrpr %g0, PIL_MAX, %pil ! disable interrupts (1-15)
1187 wrpr %g0, %g1, %pstate ! Disable vec interrupts
1197 wrpr %g0, %g5, %pstate ! Enable vec interrupts
1381 ! Enable interrupts and return
[all …]
/titanic_44/usr/src/uts/sun4u/io/px/
H A Dpx_tools_4u.c52 * px_phys_peek_4u() disables interrupts. Interrupts are reenabled at the end
57 * interrupts are reenabled.
65 * workaround can break. Also, other PIL 15 interrupts besides the ones we are
/titanic_44/usr/src/uts/i86xpv/io/psm/
H A Dxpv_psm.c243 * problem free from high level/NMI type of interrupts in xen_psm_nmi_intr()
361 * pending interrupts before retrying. in xen_psm_acquire_irq()
573 * It is called with interrupts disabled, and does not enable interrupts.
602 * If new ipl level will enable any pending interrupts, setup so the in xen_psm_setspl()
803 * Disable all device interrupts for the given cpu.
804 * High priority interrupts are not disabled and will still be serviced.
839 * Rebalance device interrupts among online processors in xen_psm_enable_intr()
876 * interrupts should be generated. There is no need to support the periodic
912 * This function will enable timer interrupts.
921 * This function will disable timer interrupts on the current cpu.

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