| /titanic_52/usr/src/uts/common/sys/ |
| H A D | pci.h | 64 #define PCI_CONF_ILINE 0x3c /* interrupt line, 1 byte */
65 #define PCI_CONF_IPIN 0x3d /* interrupt pin, 1 byte */
136 #define PCI_CBUS_ILINE 0x3c /* interrupt line, 1 byte */
137 #define PCI_CBUS_IPIN 0x3d /* interrupt pin, 1 byte */
161 * PCI Interrupt pin value
171 #define PCI_STAT_INTR 0x8 /* Interrupt state */
409 * Programming interfaces for class 0x8 / subclass 0x0 (interrupt controller)
414 #define PCI_PERIPH_PIC_IF_IO_APIC 0x10 /* I/O APIC interrupt ctrlr */
|
| /titanic_52/usr/src/cmd/lp/filter/postscript/postprint/ |
| H A D | postprint.c | 184 init_signals(); /* sets up interrupt handling */ in main()
202 void interrupt(); /* signal handler */ in init_signals()
211 if ( signal(SIGINT, interrupt) == SIG_IGN ) { in init_signals()
216 signal(SIGHUP, interrupt); in init_signals()
217 signal(SIGQUIT, interrupt); in init_signals()
220 signal(SIGTERM, interrupt); in init_signals()
|
| /titanic_52/usr/src/uts/common/io/yge/ |
| H A D | yge.c | 1008 * Allocate the interrupt. Note that we only bother with a single in yge_add_intr()
1009 * interrupt. One could argue that for MSI devices with dual ports, in yge_add_intr()
1010 * it would be nice to have a separate interrupt per port. But right in yge_add_intr()
1012 * a single interrupt. in yge_add_intr()
1019 yge_error(dev, NULL, "Unable to allocate interrupt handle"); in yge_add_intr()
1027 "Unable to allocate interrupt, %d, count %d", in yge_add_intr()
1038 "Unable to get interrupt priority, %d", rv); in yge_add_intr()
1046 "Unable to get interrupt capabilities, %d", rv); in yge_add_intr()
1053 /* register interrupt handler to kernel */ in yge_add_intr()
1058 "Unable to add interrupt handle in yge_add_intr()
[all...] |
| /titanic_52/usr/src/uts/intel/io/amr/ |
| H A D | amr.c | 379 * Allocate and connect our interrupt. in amr_attach()
383 "High level interrupt is not supported!")); in amr_attach()
393 softs->iblock_cookiep); /* should be used in interrupt */ in amr_attach()
395 softs->iblock_cookiep); /* should be used in interrupt */ in amr_attach()
397 softs->iblock_cookiep); /* should be used in interrupt */ in amr_attach()
540 /* disconnect the interrupt handler */ in amr_detach()
601 * Take an interrupt, or be poked by other code to look for interrupt-worthy
1741 * current interrupt and wait for the next one in amr_tran_reset()
2191 /* acknowledge interrupt */ in amr_done()
[all...] |
| H A D | amrreg.h | 183 /* polling/interrupt-driven */
185 /* polling/interrupt-driver */
652 #define AMR_STOGGLE 0x11 /* interrupt enable bit here */
658 #define AMR_SINTR 0x1a /* interrupt status */
|
| /titanic_52/usr/src/uts/common/io/afe/ |
| H A D | afe.c | 406 /* get the interrupt block cookie */ in afe_attach()
435 * Initialize interrupt kstat. This should not normally fail, since in afe_attach()
507 * Establish interrupt handler. in afe_attach()
511 afe_error(dip, "unable to add interrupt"); in afe_attach()
1463 /* prevent an interrupt */ in afe_stopmac()
1814 * Interrupt service routine.
1832 /* check interrupt status bits, did we interrupt? */ in afe_intr()
1840 /* ack the interrupt */ in afe_intr()
1936 * interrupt in afe_enableinterrupts()
[all...] |
| /titanic_52/usr/src/uts/sun4u/io/px/ |
| H A D | px_err.c | 473 /* LPU Link Interrupt Table */
486 /* LPU Physical Interrupt Table */
499 /* LPU Receive Interrupt Table */
512 /* LPU Transmit Interrupt Table */
525 /* LPU LTSSM Interrupt Table */
538 /* LPU Gigablaze Glue Interrupt Table */
641 * Interrupt handler for the JBC/UBC block.
680 * Interrupt handler for the DMC/PEC block.
712 /* Set the interrupt state to idle */ in px_err_dmc_pec_intr()
744 * For readability you in code you set 1 to enable an interrupt in px_err_reg_enable()
[all...] |
| /titanic_52/usr/src/uts/common/io/usb/usba/ |
| H A D | usbai_req.c | 31 * for the control/bulk/interrupt/isoch pipes:
85 * USB_INVALID_CONTEXT - sleep in interrupt context
711 * Set USB_CB_INTR_CONTEXT callback flag if executing in interrupt context
955 * USB_CB_INTR_CONTEXT is set if called from interrupt context.
1669 * Allocate usb interrupt request
1673 * len - length of "data" for this interrupt request
1720 * create duplicate of interrupt request
1725 * len - length of "data" for this interrupt request
1838 /* Get the current interrupt pipe state */ in usb_pipe_intr_xfer()
1868 * If this is interrupt I in usb_pipe_intr_xfer()
[all...] |
| /titanic_52/usr/src/uts/common/sys/1394/adapters/ |
| H A D | hci1394_ohci.h | 526 * rollovers via the cycle 64 seconds interrupt. (NOTE: every 2
530 * We will start with the interrupt disabled, if the bus master writes
531 * to the CSR bus time register, we will enable the interrupt. These
532 * fields keep track of the rollover and whether or not the interrupt
|
| /titanic_52/usr/src/uts/sun4/os/ |
| H A D | mp_startup.c | 398 * Initialize the interrupt threads for this CPU in setup_cpu_common()
468 * Clean any machine specific interrupt states. in cleanup_cpu_common()
475 * and it's interrupt threads. Clean these up. in cleanup_cpu_common()
480 * Free the interrupt stack. in cleanup_cpu_common()
|
| /titanic_52/usr/src/lib/efcode/engine/ |
| H A D | properties.c | 663 icells = get_default_intprop(env, "#interrupt-cells", node, 1); in print_imap()
706 { "interrupt-map", print_imap },
707 { "#interrupt-cells", print_integer },
708 { "interrupt-map-mask", print_integer },
|
| /titanic_52/usr/src/uts/common/io/hxge/ |
| H A D | hxge_hw.c | 158 * This interrupt handler will have to go through in hxge_intr()
372 * This interrupt handler is for system error interrupts. in hxge_syserr_intr()
450 * processing by the receive packet interrupt routines. in hxge_rx_hw_blank()
680 "NULL ldgvp (interrupt not ready).")); in hxge_check_hw_state()
|
| H A D | hxge_impl.h | 227 * - interrupt handler function.
229 * Generic system interrupt handler with two arguments:
234 * Logical device interrupt handler with two arguments:
|
| /titanic_52/usr/src/uts/common/sys/rsm/ |
| H A D | rsmpi.h | 429 * sending side interrupt operations:
457 * receiving side interrupt operations:
661 * sending side interrupt operations:
681 * receiving side interrupt operations:
|
| /titanic_52/usr/src/uts/common/sys/scsi/adapters/pmcs/ |
| H A D | pmcs_def.h | 329 * so the interrupt code frees the work structure that has this
332 * A tag type of CBACK means that the the interrupt handler
338 * be woken up from interrupt level when the command completes
344 * interrupt code for command done notification is the setting
|
| /titanic_52/usr/src/uts/intel/io/acpica/hardware/ |
| H A D | hwgpe.c | 344 * PARAMETERS: GpeXruptInfo - GPE Interrupt info
384 * PARAMETERS: GpeXruptInfo - GPE Interrupt info
424 * PARAMETERS: GpeXruptInfo - GPE Interrupt info
475 * PARAMETERS: GpeXruptInfo - GPE Interrupt info
|
| /titanic_52/usr/src/boot/sys/boot/i386/btx/lib/ |
| H A D | btxsys.s | 30 .set INT_SYS,0x30 # Interrupt number
|
| /titanic_52/usr/src/uts/common/io/audio/drv/audioemu10k/ |
| H A D | audioemu10k.h | 229 /* Half loop interrupt registers (audigy only) */
238 /* Interrupt pending register */
251 /* Interrupt enable register */
|
| /titanic_52/usr/src/uts/common/crypto/api/ |
| H A D | kcf_digest.c | 89 * Process or interrupt, according to the semantics dictated by the 'cr'.
330 * Process or interrupt, according to the semantics dictated by the 'cr'.
379 * Process or interrupt, according to the semantics dictated by the 'cr'.
|
| /titanic_52/usr/src/uts/common/io/ath/ |
| H A D | ath_impl.h | 74 #define ATH_DBG_INT 0x00000008 /* interrupt handler */
249 uint_t axq_intrcnt; /* interrupt count */
307 HAL_INT asc_imask; /* interrupt mask copy */
|
| /titanic_52/usr/src/cmd/cmd-inet/usr.bin/telnet/ |
| H A D | externs.h | 103 extern int localchars; /* we recognize interrupt/quit */
110 extern int autosynch; /* send interrupt characters with SYNCH? */
131 extern boolean_t intr_happened; /* for interrupt handling */
|
| /titanic_52/usr/src/uts/intel/ia32/os/ |
| H A D | desctbls.c | 105 gate_desc_t *idt0; /* interrupt descriptor table */
312 * Install gate segment descriptor for interrupt, trap, call and task gates.
437 * Is this an interrupt gate? in xen_idt_to_trap_info()
906 * Note that for amd64 we pretty much require every gate to be an interrupt
912 * ensue. We also use interrupt gates for i386 as well even though this is not
998 * Install the DTrace interrupt handler for the pid provider. in init_idt_common()
1332 * interrupt gate above. in brand_interpositioning_enable()
|
| /titanic_52/usr/src/uts/common/io/igb/ |
| H A D | igb_gld.c | 709 * Enable interrupt on the specificed rx ring.
720 /* Interrupt enabling for MSI-X */ in igb_rx_ring_intr_enable()
726 /* Interrupt enabling for MSI and legacy */ in igb_rx_ring_intr_enable()
737 * Disable interrupt on the specificed rx ring.
748 /* Interrupt disabling for MSI-X */ in igb_rx_ring_intr_disable()
755 /* Interrupt disabling for MSI and legacy */ in igb_rx_ring_intr_disable()
1571 /* Set interrupt throttling rate */ in igb_set_priv_prop()
|
| /titanic_52/usr/src/uts/common/io/ |
| H A D | emul64.c | 657 * Can be called by interrupt thread.
731 * Can be called by interrupt thread.
805 * Can be called by interrupt thread.
882 * Can be called by interrupt thread.
913 * Can be called by interrupt thread.
928 * Can be called by interrupt thread.
995 * Can be called by interrupt thread.
|
| /titanic_52/usr/src/grub/grub-0.97/netboot/ |
| H A D | via-rhine.c | 593 dev->tbusy flag. The other thread is the interrupt handler, which is single
594 threaded by the hardware and interrupt handling software.
601 The interrupt handler has exclusive control over the Rx ring and records stats
868 /* Bits in the interrupt status/mask registers. */
889 /* Enable interrupts by setting the interrupt mask. */ in rhine_irq()
1212 /* Acknowledge all of the current interrupt sources ASAP. */ in rhine_poll()
1240 /* Acknowledge all of the current interrupt sources ASAP. */ in rhine_poll()
|