| /titanic_53/usr/src/uts/i86pc/ml/ |
| H A D | syscall_asm_amd64.s | 136 * | 24 | user (or interrupt) stack pointer |
150 * the stack pointer points at the state saved when we took the interrupt:
174 * The interrupt stack pointer we saved on entry to the BRAND_CALLBACK macro
379 * In particular, we have a stack structure like that for interrupt
987 * Set the interrupt flag before storing the flags to the
1164 * This is the destination of the "int $T_SYSCALLINT" interrupt gate, used by
1222 * interrupt flag bit, so an interrupt can run us just after the lcall
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| /titanic_53/usr/src/cmd/plimit/ |
| H A D | plimit.c | 50 static int interrupt; variable
164 while (--argc >= 0 && !interrupt) { in main()
215 if (interrupt) in main()
223 interrupt = sig; in intr()
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| /titanic_53/usr/src/uts/intel/io/acpica/resources/ |
| H A D | rsdumpinfo.c | 76 …{ACPI_RSD_UINT8 , ACPI_RSD_OFFSET (Irq.InterruptCount), "Interrupt Count", …
77 …{ACPI_RSD_SHORTLIST,ACPI_RSD_OFFSET (Irq.Interrupts[0]), "Interrupt List", …
221 …{ACPI_RSD_UINT8, ACPI_RSD_OFFSET (ExtendedIrq.InterruptCount), "Interrupt Count", …
222 …{ACPI_RSD_DWORDLIST,ACPI_RSD_OFFSET (ExtendedIrq.Interrupts[0]), "Interrupt List", …
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| /titanic_53/usr/src/uts/common/sys/ib/adapters/hermon/ |
| H A D | hermon.h | 103 #define HERMON_MSIX_MAX 256 /* max # of interrupt vectors */
316 * interrupt once all EQs have been serviced.
373 /* Hermon interrupt/MSI information */
478 * well as their corresponding "clear" registers) for interrupt
505 * Hermon interrupt mailbox lists. We allocate both an "In" mailbox
506 * and an "Out" type mailbox for the interrupt context. This is in
508 * the interrupt context, and we can NOSLEEP without having to worry
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| /titanic_53/usr/src/uts/common/sys/fibre-channel/fca/emlxs/ |
| H A D | emlxs_messages.h | 629 "attention interrupt.", \
650 "attention interrupt.", \
661 "attention interrupt.", \
671 "This indicates that an interrupt has occurred and the " \
717 "This indicates that an interrupt has occurred indicating " \
891 "Stray mailbox interrupt.", \
894 "This indicates that a mailbox command completion interrupt " \
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| /titanic_53/usr/src/uts/sun4u/io/ |
| H A D | upa64s.c | 568 * Translate the UPA devices interrupt property. This is the only case I
570 * just use UPA_BASE_INO as our interrupt value and add to it the upa port id.
626 * Make sure an interrupt handler isn't already installed. in upa64s_add_intr_impl()
645 * Enable the interrupt through its interrupt mapping register. in upa64s_add_intr_impl()
1166 * to support interrupt distribution on sun4u systems. When this
1167 * function is called by the interrupt distribution framework, it will
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| /titanic_53/usr/src/cmd/hal/hald/ |
| H A D | ids.c | 573 /* interrupt controllers */
574 {"PNP0000", "AT Interrupt Controller"},
575 {"PNP0001", "EISA Interrupt Controller"},
576 {"PNP0002", "MCA Interrupt Controller"},
578 {"PNP0004", "Cyrix SLiC MP interrupt controller"},
683 {"PNP0C03", "Plug and Play BIOS Event Notification Interrupt"},
695 {"PNP0C0F", "PCI interrupt link device"},
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| /titanic_53/usr/src/uts/sun4v/io/niumx/ |
| H A D | niumx.c | 162 * This driver uses the old interrupt routines which are supported in _init()
226 "pending interrupt (%x,%lx) timedout\n", in niumx_intr_dist()
293 /* add interrupt redistribution callback */ in niumx_attach()
1013 "pending interrupt (%x,%lx) timedout\n", in niumx_set_intr_target()
1102 /* Restore orig. interrupt handler & args in handle. */ in niumx_add_intr()
1162 "pending interrupt (%x,%lx) timedout\n", in niumx_rem_intr()
1180 * niumx_intr_hdlr (our interrupt handler)
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| /titanic_53/usr/src/cmd/ptools/pmadvise/ |
| H A D | pmadvise.c | 264 * We bail out as soon as possible when interrupt is set
266 static int interrupt = 0; variable
269 * Interrupt handler
568 if (interrupt) in create_maplist()
671 while (!interrupt && psaddr != NULL) { in apply_advice()
932 interrupt++; in intr()
1038 while (!interrupt && argc-- > 0) { in main()
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| /titanic_53/usr/src/uts/sun4u/starcat/ml/ |
| H A D | drmach_asm.s | 575 ! interrupt vector, then updates the processor's LPA and
578 ! The special interrupt vector is assumed to be a cross-call to
580 ! the copy-rename operation. The interrupt is received and discarded;
582 ! the Interrupt Receive Status Register is employed, temporarily,
736 ! Loop on IRSR waiting for interrupt. The expected interrupt
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| /titanic_53/usr/src/uts/common/io/ntxn/ |
| H A D | unm_inc.h | 1073 * Interrupt Register definition
1292 * Tell which interrupt source we want to operate on.
1308 * PCIX Interrupt Mask Register.
1421 * List the bit positions in the registers of the interrupt sources.
1462 UNM_I2Q_SRC_SRE_EPG = 40, /* SRE/EPG aggregate interrupt */
1471 UNM_I2Q_SRC_MAX = 47, /* max used interrupt line */
1476 * Interrupt Source Enable/Clear registers for the I2Q.
1488 * List the possible interrupt sources and the
1527 * Interrupt enables and interrupt status for all 16 queues in a group.
1535 * Control operation for an SQM Group interrupt.
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| /titanic_53/usr/src/uts/common/io/ |
| H A D | ecpp.c | 135 * - interrupt occurs, ecpp_isr() checks if all the data was transferred, if so
141 * interrupt; ecpp_isr() will then look if there is more data and if so
142 * triggers the soft interrupt, which transfers the next byte. PIO method
155 * (and also nAck in Nibble Mode) which results in an interrupt on the host;
3057 * interrupt may occur while other thread is holding the lock in ecpp_isr()
3059 * since it cannot cancel the interrupt thread, in ecpp_isr()
3061 * telling interrupt handler to exit immediately in ecpp_isr()
3116 * check if interrupt is for this device: in ecpp_isr()
3127 * so if DSR is read after interrupt occured, but before in ecpp_isr()
3129 * as a result, we can miss a service interrupt in PIO mode in ecpp_isr()
[all …]
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| /titanic_53/usr/src/man/man1/ |
| H A D | postio.1 | 130 overrides many other options. To exit interactive mode use your interrupt or
185 sequence of \fB^T\fR (status query), \fB^C\fR (interrupt), and \fB^D\fR (end
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| /titanic_53/usr/src/uts/common/sys/nxge/ |
| H A D | nxge_ipp_hw.h | 104 /* IPP Interrupt Status Registers */
225 /* IPP Interrupt Mask Registers */
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| /titanic_53/usr/src/uts/intel/ia32/sys/ |
| H A D | privregs.h | 152 * Macros for saving all registers necessary on interrupt entry,
211 * interrupt gate handler, i.e. interrupts are -already- disabled.
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| /titanic_53/usr/src/uts/sun4u/sys/ |
| H A D | sbbcvar.h | 54 dev_info_t *dip; /* Interrupt parent dip */
107 ddi_iblock_cookie_t sbbc_iblock_cookie; /* interrupt block cookie */
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| H A D | upa64s.h | 42 * of a UPA port interrupt.
53 * Interrupt Mapping Registers
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| /titanic_53/usr/src/uts/i86pc/sys/ |
| H A D | smp_impldefs.h | 76 extern int (*slvltovect)(int); /* ipl interrupt priority level */
94 extern void av_set_softint_pending(); /* set software interrupt pending */
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| /titanic_53/usr/src/cmd/power/ |
| H A D | pm_pam_conv.c | 52 interrupt(int x) in interrupt() function
76 sig = signal(SIGINT, interrupt); in getinput()
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| /titanic_53/usr/src/uts/common/io/hxge/ |
| H A D | hpi_vir.c | 141 * Set interrupt timer and arm bit.
203 * Set the system interrupt data.
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| /titanic_53/usr/src/uts/common/io/fibre-channel/fca/emlxs/ |
| H A D | emlxs_sli3.c | 818 * Add our interrupt routine to kernel's interrupt chain & enable it in emlxs_sli3_online()
824 "Unable to add interrupt(s)."); in emlxs_sli3_online()
1365 "Attempting single interrupt mode..."); in emlxs_sli3_online()
1375 "Unable to initialize interrupt. status=%d", in emlxs_sli3_online()
1571 * At this point, the interrupt will be generated by the HW in emlxs_sli3_online()
1600 * Enable link attention interrupt in emlxs_sli3_online()
3201 /* If interrupt is enabled, use sleep, otherwise poll */ in emlxs_sli3_issue_mbox_cmd()
3374 /* Interrupt board to do it right away */ in emlxs_sli3_issue_mbox_cmd()
4250 /* Check for legacy interrupt handling */ in emlxs_sli3_msi_intr()
4280 /* Process the interrupt */ in emlxs_sli3_msi_intr()
[all …]
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| /titanic_53/usr/src/uts/common/io/hotplug/pcihp/ |
| H A D | pcihp.c | 219 * bit to be set causing an extra interrupt. Although the cPCI specifications
2347 * All the events that may be handled in interrupt context should be in pcihp_event_handler()
2354 * Check and clear ENUM# interrupt status. This may be in pcihp_event_handler()
2358 * In such cases, the intent is to clear interrupt and in pcihp_event_handler()
2359 * process the interrupt in non-interrupt context. in pcihp_event_handler()
2367 /* this is the only event coming through in interrupt context */ in pcihp_event_handler()
2761 * slot. Please note that the interrupt is already cleared. in pcihp_event_handler()
2789 * necessarily be invokable in interrupt context. in pcihp_event_handler()
3195 * delivery of interrupt by the framework.
3198 * PCIHP_CLEAR_ENUM = just clear interrupt and return the PCI device no. if
[all …]
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| /titanic_53/usr/src/uts/intel/io/acpica/events/ |
| H A D | evglock.c | 162 * release interrupt occurs. If there is actually a pending
294 * released interrupt. in AcpiEvAcquireGlobalLock()
303 * Wait for handshake with the global lock interrupt handler. in AcpiEvAcquireGlobalLock()
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| /titanic_53/usr/src/man/man9f/ |
| H A D | kmem_cache_create.9f | 576 from interrupt context. \fBkmem_cache_create()\fR can also block for available
580 \fBkmem_cache_alloc()\fR can be called from interrupt context only if the
585 \fBkmem_cache_free()\fR can be called from user, kernel, or interrupt context.
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| /titanic_53/usr/src/uts/common/io/rtls/ |
| H A D | rtls.h | 171 uint16_t int_mask; /* interrupt mask */
331 * Interrupt register
471 * Multiple interrupt select register
|