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/linux/Documentation/devicetree/bindings/gpio/
H A Dgpio-thunderx.txt12 - interrupt-controller: Marks the device node as an interrupt controller.
13 - #interrupt-cells: Must be present and have value of 2 if
14 "interrupt-controller" is present.
25 interrupt-controller;
26 #interrupt-cells = <2>;
/linux/arch/mips/boot/dts/mscc/
H A Djaguar2.dtsi29 cpuintc: interrupt-controller {
31 #interrupt-cells = <1>;
32 interrupt-controller;
33 compatible = "mti,cpu-interrupt-controller";
56 interrupt-parent = <&intc>;
63 intc: interrupt-controller@70000070 {
66 #interrupt-cells = <1>;
67 interrupt-controller;
68 interrupt-parent = <&cpuintc>;
/linux/arch/m68k/include/asm/
H A Dm54xxsim.h22 * Interrupt Controller Registers
24 #define MCFICM_INTC0 (MCF_MBAR + 0x700) /* Base for Interrupt Ctrl 0 */
26 #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
27 #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
28 #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
29 #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
30 #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
31 #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
79 #define MCFEPORT_EPIER (MCF_MBAR + 0xf05) /* Interrupt enable */
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmicrochip,mcp23s08.yaml37 interrupt-controller: true
39 '#interrupt-cells':
63 Sets the mirror flag in the IOCON register. Devices with two interrupt
66 have two different interrupt outputs One for bank 1 and another for
68 the bank that an input change occurred on. If it is not set,the interrupt
115 #include <dt-bindings/interrupt-controller/irq.h>
128 interrupt-parent = <&gpio1>;
130 interrupt-controller;
131 #interrupt-cells = <2>;
H A Dawinic,aw9523-pinctrl.yaml14 I/O, 256 steps PWM mode and interrupt support.
34 interrupt-controller: true
40 '#interrupt-cells':
43 include/dt-bindings/interrupt-controller/irq.h
104 #include <dt-bindings/interrupt-controller/irq.h>
113 interrupt-parent = <&tlmm>;
118 interrupt-controller;
119 #interrupt-cells = <2>;
H A Dcypress,cy8c95x0.yaml37 interrupt-controller: true
39 '#interrupt-cells':
111 - interrupt-controller
112 - '#interrupt-cells'
123 #include <dt-bindings/interrupt-controller/arm-gic.h>
124 #include <dt-bindings/interrupt-controller/irq.h>
135 #interrupt-cells = <2>;
137 interrupt-controller;
/linux/arch/arm64/boot/dts/cavium/
H A Dthunder2-99xx.dtsi10 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 interrupt-parent = <&gic>;
58 gic: interrupt-controller@4000080000 {
60 #interrupt-cells = <3>;
64 interrupt-controller;
100 #interrupt-cells = <1>;
117 interrupt-map-mask = <0 0 0 7>;
118 interrupt-map =
137 interrupt-parent = <&gic>;
/linux/Documentation/hid/
H A Dintel-thc-hid.rst22 Unlike other common SPI/I2C controllers, THC handles the HID device data interrupt and reset
110 the registers include several categories: Interrupt status and control, DMA configure,
120 Touch ICs interrupt and start DMA receive/send data from/to Touch ICs according to interrupt
126 SPI bus and I2C bus. THC also integrates a GPIO controller to provide interrupt line support
183 THC also includes two GPIO pins, one for interrupt and the other for device reset control.
185 Interrupt line can be configured to either level triggered or edge triggered by setting MMIO
206 2.4 Interrupt delay
209 Because of MCU performance limitation, some touch devices cannot de-assert interrupt pin
210 immediately after input data is transferred, which cause an interrupt toggle delay. But THC
211 always detects next interrupt immediately after last input interrupt is handled. In this
[all …]
/linux/arch/arm/boot/dts/st/
H A Dstm32f4-pinctrl.dtsi52 interrupt-parent = <&exti>;
58 interrupt-controller;
59 #interrupt-cells = <2>;
68 interrupt-controller;
69 #interrupt-cells = <2>;
78 interrupt-controller;
79 #interrupt-cells = <2>;
88 interrupt-controller;
89 #interrupt-cells = <2>;
98 interrupt-controller;
[all …]
H A Dste-href-tvk1281618-r3.dtsi7 #include <dt-bindings/interrupt-controller/irq.h>
32 interrupt-parent = <&gpio2>;
37 interrupt-controller;
38 #interrupt-cells = <1>;
45 interrupt-controller;
46 #interrupt-cells = <2>;
87 interrupt-parent = <&gpio2>;
101 // This interrupt is not properly working with the driver
102 // interrupt-parent = <&gpio1>;
139 interrupt-parent = <&gpio2>;
[all …]
/linux/arch/powerpc/boot/dts/
H A Dkmeter1.dts62 interrupt-parent = <&ipic>;
72 interrupt-parent = <&ipic>;
83 interrupt-parent = <&ipic>;
92 interrupt-parent = <&ipic>;
98 interrupt-parent = <&ipic>;
104 interrupt-parent = <&ipic>;
110 interrupt-parent = <&ipic>;
116 interrupt-parent = <&ipic>;
123 #interrupt-cells = <2>;
125 interrupt-controller;
[all …]
H A Dcurrituck.dts67 MPIC: interrupt-controller {
69 interrupt-controller;
73 #interrupt-cells = <2>;
102 interrupt-parent = <&MPIC>;
114 interrupt-parent = <&MPIC>;
127 #interrupt-cells = <1>;
155 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
156 interrupt-map = <
165 #interrupt-cells = <1>;
192 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
[all …]
/linux/arch/arm64/boot/dts/hisilicon/
H A Dhip07.dtsi8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&gic>;
940 gic: interrupt-controller@4d000000 {
942 #interrupt-cells = <3>;
946 interrupt-controller;
1065 p0_mbigen_peri_b: interrupt-controller@60080000 {
1071 interrupt-controller;
1072 #interrupt-cells = <2>;
1077 p0_mbigen_pcie_a: interrupt-controller@a0080000 {
1083 interrupt-controller;
[all …]
/linux/drivers/gpu/drm/amd/include/ivsrcid/nbio/
H A Dirqsrcs_nbif_7_4.h30 #define NBIF_7_4__SRCID__DOORBELL_INTERRUPT 0x5F // Interrupt for doorbell event …
31 #define NBIF_7_4__SRCID__RAS_CONTROLLER_INTERRUPT 0x60 // Interrupt for ras_intr_valid …
32 #define NBIF_7_4__SRCID__ERREVENT_ATHUB_INTERRUPT 0x61 // Interrupt for SDP ErrEvent re…
33 … 0x87 // Valid message in PF->VF mailbox message buffer (The interrupt is sent on behal…
34 …x88 // Acknowledge message in PF->VF mailbox message buffer (The interrupt is sent on behal…
35 … 0x89 // Valid message in VF->PF mailbox message buffer (The interrupt is sent on behal…
36 …x8A // Acknowledge message in VF->PF mailbox message buffer (The interrupt is sent on behal…
/linux/Documentation/devicetree/bindings/rtc/
H A Ds3c-rtc.yaml48 Two interrupt numbers to the cpu should be specified. First
49 interrupt number is the rtc alarm interrupt and second interrupt number
50 is the rtc tick interrupt. The number of cells representing a interrupt
51 depends on the parent interrupt controller.
/linux/Documentation/devicetree/bindings/thermal/
H A Dqcom-lmh.yaml36 '#interrupt-cells':
39 interrupt-controller: true
65 - '#interrupt-cells'
66 - interrupt-controller
76 #include <dt-bindings/interrupt-controller/arm-gic.h>
86 interrupt-controller;
87 #interrupt-cells = <1>;
/linux/Documentation/devicetree/bindings/mfd/
H A Dmaxim,max77759.yaml26 interrupt-controller: true
28 "#interrupt-cells":
49 #include <dt-bindings/interrupt-controller/irq.h>
60 interrupt-controller;
61 #interrupt-cells = <2>;
69 interrupt-controller;
70 #interrupt-cells = <2>;
/linux/arch/arm64/boot/dts/st/
H A Dstm32mp251.dtsi7 #include <dt-bindings/interrupt-controller/arm-gic.h>
33 interrupt-affinity = <&cpu0>;
34 interrupt-parent = <&intc>;
61 interrupt-parent = <&intc>;
117 intc: interrupt-controller@4ac00000 {
119 #interrupt-cells = <3>;
120 interrupt-controller;
148 interrupt-parent = <&intc>;
160 interrupt-parent = <&intc>;
298 interrupt-names = "global";
[all …]
/linux/arch/m68k/coldfire/
H A Dintc-2.c4 * General interrupt controller code for the many ColdFire cores that use
5 * interrupt controllers with 63 interrupt sources, organized as 56 fully-
6 * programmable + 7 fixed-level interrupt sources. This includes the 523x
23 #include <linux/interrupt.h>
41 #define EINT1 65 /* EDGE Port interrupt 1 */
42 #define EINT7 71 /* EDGE Port interrupt 7 */
106 * traditional priority interrupt scheme of the m68k/ColdFire. This
107 * only needs to be set once for an interrupt, and we will never change
136 /* Set EPORT line as interrupt source */ in intc_irq_startup()
197 /* Mask all interrupt sources */ in init_IRQ()
/linux/drivers/scsi/
H A Dfdomain.h36 #define ASTAT_IRQ BIT(0) /* Interrupt active */
44 #define REG_ICTL 2 /* W: Interrupt Control */
61 #define REG_INTCOND 4 /* R: Interrupt Condition - (@) */
62 #define IRQ_FIFO BIT(1) /* FIFO interrupt */
63 #define IRQ_REQ BIT(2) /* SCSI Request interrupt */
64 #define IRQ_SEL BIT(3) /* SCSI Select interrupt */
65 #define IRQ_ARB BIT(4) /* SCSI Arbitration interrupt */
66 #define IRQ_RST BIT(5) /* SCSI Reset interrupt */
67 #define IRQ_FORCED BIT(6) /* Forced interrupt */
71 #define ACTL_FIRQ BIT(1) /* Set Forced interrupt */
[all …]
/linux/arch/arm64/boot/dts/bitmain/
H A Dbm1880.dtsi8 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
82 gic: interrupt-controller@50001000 {
87 interrupt-controller;
88 #interrupt-cells = <3>;
132 interrupt-controller;
133 #interrupt-cells = <2>;
150 interrupt-controller;
151 #interrupt-cells = <2>;
168 interrupt-controller;
[all …]
/linux/Documentation/devicetree/bindings/arm/tegra/
H A Dnvidia,tegra186-pmc.yaml34 interrupt-controller: true
36 "#interrupt-cells":
38 interrupt source. The value must be 2.
41 nvidia,invert-interrupt:
42 description: If present, inverts the PMU interrupt signal.
168 interrupt-controller: ['#interrupt-cells']
169 "#interrupt-cells":
171 - interrupt-controller
176 #include <dt-bindings/interrupt-controller/arm-gic.h>
188 nvidia,invert-interrupt;
H A Dnvidia,tegra194-cbb.yaml26 SError or Data Abort is masked and the error is reported with interrupt.
33 In addition, an interrupt is also generated to CCPLEX. These initiators
59 CCPLEX receives secure or nonsecure interrupt depending on error type.
60 A secure interrupt is received for SEC(firewall) & SLV errors and a
61 non-secure interrupt is received for TMO & DEC errors.
63 - description: non-secure interrupt
64 - description: secure interrupt
88 #include <dt-bindings/interrupt-controller/arm-gic.h>
/linux/arch/arm/boot/dts/socionext/
H A Dmilbeaut-m10v.dtsi2 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 interrupt-parent = <&gic>;
58 interrupt-parent = <&gic>;
60 gic: interrupt-controller@1d000000 {
62 interrupt-controller;
63 #interrupt-cells = <3>;
87 interrupt-names = "rx", "tx";
/linux/Documentation/devicetree/bindings/pci/
H A Dsamsung,exynos-pcie.yaml73 - "#interrupt-cells"
74 - interrupt-map
75 - interrupt-map-mask
91 #include <dt-bindings/interrupt-controller/irq.h>
92 #include <dt-bindings/interrupt-controller/arm-gic.h>
101 #interrupt-cells = <1>;
116 interrupt-map-mask = <0 0 0 0>;
117 interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;

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