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/titanic_53/usr/src/uts/sun4/sys/
H A Divintr.h36 /* Software interrupt and other bit flags */
37 #define IV_SOFTINT_PEND 0x1 /* Software interrupt is pending */
38 #define IV_SOFTINT_MT 0x2 /* Multi target software interrupt */
42 * Reserve some interrupt vector data structures for the hardware and software
46 * Need one single target software interrupt per cpu for tick accounting.
64 /* Software interrupt type */
71 * Interrupt Vector Structure.
73 * Interrupt vector structure is allocated either from the reserved pool or
81 ushort_t iv_inum; /* MDB: interrupt mondo number */
82 ushort_t iv_pil; /* Interrupt priority level */
[all …]
/titanic_53/usr/src/uts/sun4/ml/
H A Dinterrupt.s55 * (TT 0x40..0x4F, TL>0) Interrupt Level N Handler (N == 1..15)
57 * %g4 - interrupt request level
99 wr %g5, CLEAR_SOFTINT ! clear interrupt on this pil
126 ! clear the iv_pending flag for this interrupt request
138 ! %g1 - interrupt handler at TL==0
168 .asciz "!interrupt 0x%x at level %d not serviced"
192 * so, there is another interrupt to process. The caller must call
196 * and other actions which need to occur after invocation of an interrupt
204 * os3 - if set, another interrupt needs to be processed
346 * Handle an interrupt in a new thread.
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/titanic_53/usr/src/uts/common/sys/usb/hcd/openhci/
H A Dohcid.h50 * OpenHCI interrupt status information structure
54 * interrupt tables etc.. for the normal and polled modes. In addition,
55 * suppose if we switched to polled mode while ohci interrupt handler is
56 * executing in the normal mode then we need to save the interrupt status
57 * information that includes interrupts for which ohci interrupt handler
66 * in the ohci interrupt handler to indicate that currently ohci
67 * interrupt handler is in execution and also while critical code
68 * execution within the ohci interrupt handler. These flags will
70 * interrupt status information.
75 * The following fields will be used to save the interrupt status
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/titanic_53/usr/src/uts/sun4/os/
H A Dintr.c53 /* Global locks which protect the interrupt distribution lists */
57 /* Head of the interrupt distribution lists */
61 static uint64_t siron_inum[DDI_IPL_10]; /* software interrupt numbers */
81 * bug in setsoftint(exhaustion of interrupt pool free list).
92 * allowed to queue a soft interrupt. It is softint()'s job to ensure
97 static int siron_pending[DDI_IPL_10]; /* software interrupt pending flags */
100 int intr_policy = INTR_WEIGHTED_DIST; /* interrupt distribution policy */
108 * intr_init() - Interrupt initialization
109 * Initialize the system's interrupt vector table.
140 * A soft interrupt may have been requested prior to the initialization in intr_init()
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/titanic_53/usr/src/uts/sun4u/opl/io/pcicmu/
H A Dpcmu_ib.c28 * CMU-CH Interrupt Block
53 * Allocate interrupt block state structure and link it to in pcmu_ib_create()
63 * Determine virtual addresses of interrupt mapping, clear and diag in pcmu_ib_create()
130 * Determine the cpu for the interrupt. in pcmu_ib_intr_enable()
144 * Disable the interrupt via its interrupt mapping register.
146 * If called under interrupt context, wait should be set to 0
157 /* disable the interrupt */ in pcmu_ib_intr_disable()
169 /* busy wait if there is interrupt being processed */ in pcmu_ib_intr_disable()
175 * to prevent declaring an interrupt timeout. The in pcmu_ib_intr_disable()
176 * master-interrupt mechanism in OBP should deliver in pcmu_ib_intr_disable()
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/titanic_53/usr/src/boot/sys/boot/fdt/dts/powerpc/
H A Dp1020rdb.dts81 interrupt-parent = <&mpic>;
210 interrupt-parent = <&mpic>;
216 interrupt-parent = <&mpic>;
227 interrupt-parent = <&mpic>;
242 interrupt-parent = <&mpic>;
253 interrupt-parent = <&mpic>;
263 interrupt-parent = <&mpic>;
273 interrupt-parent = <&mpic>;
327 interrupt-parent = <&mpic>;
336 interrupt-parent = <&mpic>;
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/titanic_53/usr/src/boot/sys/boot/fdt/dts/arm/
H A Dsun4i-a10.dtsi36 interrupt-parent = <&AINTC>;
49 AINTC: interrupt-controller@01c20400 {
51 interrupt-controller;
53 #interrupt-cells = <1>;
75 interrupt-parent = <&AINTC>;
91 interrupt-parent = <&AINTC>;
109 interrupt-parent = <&AINTC>;
116 interrupt-parent = <&AINTC>;
123 interrupt-parent = <&AINTC>;
131 interrupt-parent = <&AINTC>;
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H A Drk3188.dtsi34 interrupt-parent = <&GIC>;
47 GIC: interrupt-controller@1013d000 {
51 interrupt-controller;
52 #interrupt-cells = <1>;
77 interrupt-parent = <&GIC>;
132 interrupt-parent = <&GIC>;
141 interrupt-parent = <&GIC>;
150 interrupt-parent = <&GIC>;
159 interrupt-parent = <&GIC>;
166 interrupt-parent = <&GIC>;
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H A Dannapurna-alpine.dts110 MPIC: interrupt-controller {
114 interrupt-controller;
116 #interrupt-cells = <3>;
131 interrupt-parent = <&MPIC>;
147 interrupt-parent = <&MPIC>;
153 interrupt-parent = <&MPIC>;
163 interrupt-parent = <&MPIC>;
172 interrupt-parent = <&MPIC>;
173 interrupt-map-mask = <0xf800 0 0 7>;
174 interrupt-map = <0x3000 0 0 1 &MPIC 0 32 4>, // USB adapter
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H A Dsocfpga.dtsi38 interrupt-parent = <&GIC>;
55 GIC: interrupt-controller@fffed000 {
59 interrupt-controller;
60 #interrupt-cells = <1>;
71 interrupt-parent = < &GIC >;
99 interrupt-parent = <&GIC>;
137 interrupt-parent = <&GIC>;
148 interrupt-parent = <&GIC>;
158 interrupt-parent = <&GIC>;
166 interrupt-parent = <&GIC>;
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H A Ddb88f6281.dts113 interrupt-controller;
115 #interrupt-cells = <1>;
124 interrupt-parent = <&PIC>;
164 interrupt-parent = <&PIC>;
178 interrupt-parent = <&PIC>;
190 interrupt-parent = <&PIC>;
210 interrupt-parent = <&PIC>;
219 interrupt-parent = <&PIC>;
226 interrupt-parent = <&PIC>;
235 interrupt-parent = <&PIC>;
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/titanic_53/usr/src/man/man9f/
H A Dddi_intr_get_supported_types.9f9 interrupt types
41 Pointer to supported interrupt types
47 The \fBddi_intr_get_supported_types()\fR function retrieves the interrupt types
55 returns only the interrupt types that are supported by all the hardware in the
59 An interrupt type is usable by the hardware device if it is returned by the
61 programmed to use one of the returned interrupt types to receive hardware
99 kernel non-interrupt context.
129 driver even at any time if the driver has added an interrupt handler for a
130 given interrupt type.
H A Dusb_pipe_open.9f109 \fBInterrupt pipe\fR
113 with bounded service periods, as for interrupt handling. Unidirectional.
124 transfers. Interrupt and isochronous data are together guaranteed 90% of frame
132 (See \fBusb_ep_descr\fR(9S)). Opens to interrupt and isochronous pipes can fail
136 The polling interval for periodic (interrupt or isochronous) pipes, carried by
151 are opened successfully. Interrupt and isochronous pipes have guaranteed
154 which address isochronous and interrupt transfers.) Opens of interrupt and
243 Insufficient bandwidth available. (isochronous and interrupt pipes).
252 Called from interrupt handler with USB_FLAGS_SLEEP set.
280 Isochronous or interrupt endpoint with maximum packet size of zero is not
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H A Dddi_intr_set_nreq.9f50 The \fInreq\fR parameter is the total number of interrupt resources that this
52 parameter includes any interrupt resources already allocated by the driver. For
67 can process actions related to changes in interrupt availability. See
99 the system must have interrupt pools implemented.
114 These functions can be called from kernel, non-interrupt context.
141 The Interrupt Resource Management feature is limited to device driver instances
142 that are using MSI-X interrupts (interrupt type \fBDDI_INTR_TYPE_MSIX\fR).
152 increased I/O load, the driver may want to request additional interrupt
154 return extra interrupt resources back to the system.
H A Dddi_intr_get_nintrs.9f9 supported or available for a given interrupt type
49 Interrupt type
80 Interrupt type
113 The hardware device may support more than one interrupt and can request that
152 On not finding any interrupts for the given interrupt type.
168 be called from either user or kernel non-interrupt context.
197 be called at any time, even if the driver has added an interrupt handler for a
198 given interrupt specification.
203 number of interrupts available for each interrupt priority on the system. In
/titanic_53/usr/src/uts/sun4u/serengeti/sys/
H A Dsgsbbc_priv.h57 * SBBC Interrupt registers
66 * EPLD Interrupt Register Offset for communication with the SC
91 * Port Interrupt Enable Register
97 * interrupt lines for Port Interrupt
99 * corresponds to PCI Interrupt D,
100 * bit 4 corresponds to PCI Interrupt A.
103 #define SBBC_PCI_ENABLE_INT_A 0x11 /* Enable both PCI Interrupt A */
130 sbbc_intrfunc_t sbbc_handler; /* interrupt handler */
131 caddr_t sbbc_arg; /* interrupt argument */
162 uint32_t *port_int_regs; /* interrupt regs */
[all …]
/titanic_53/usr/src/uts/common/io/cpqary3/
H A Dcpqary3_isr.c22 * interrupt.
24 * we clear the interrupt.
31 * [We either CLAIM the interrupt or Discard it]
85 * For the performant mode, we clear the interrupt in cpqary3_hw_isr()
125 * If s/w interrupt handler is already running, do not trigger another in cpqary3_hw_isr()
127 * Else, Set swintr_flag to state to the s/w interrupt handler in cpqary3_hw_isr()
129 * trigger the s/w interrupt handler in cpqary3_hw_isr()
130 * Claim the interrupt in cpqary3_hw_isr()
153 * software interrupt handler was triggered by its
154 * respective h/w interrupt handler and if affermative
[all …]
/titanic_53/usr/src/uts/sun4/io/px/
H A Dpx_ib.h41 * interrupt block soft state structure:
43 * Each px node may share an interrupt block structure with its peer
44 * node or have its own private interrupt block structure.
57 * ih structure: one per every consumer of each ino and pil pair with interrupt
62 uint32_t ih_inum; /* interrupt number for this device */
63 uint_t (*ih_handler)(); /* interrupt handler */
64 caddr_t ih_handler_arg1; /* interrupt handler argument #1 */
65 caddr_t ih_handler_arg2; /* interrupt handler argument #2 */
70 uint8_t ih_intr_flags; /* interrupt handler status flags */
82 /* Only used for MSI/X to track interrupt handler status */
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H A Dpx_intr.c26 * PX nexus interrupt handling:
27 * PX device interrupt handler wrapper
29 * PX device interrupt related initchild code
49 * interrupt jabber:
51 * When an interrupt line is jabbering, every time the state machine for the
58 * idled when an interrupt line is jabbering. See the comment at the
59 * beginning of px_intr_wrapper() explaining how the 'interrupt jabber
66 * If the unclaimed interrupt count has reached the limit set by
68 * on this ino is blocked by not idling the interrupt state machine.
100 err_fmt_str = "!%s%d: spurious interrupt from ino 0x%x"; in px_spurintr()
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/titanic_53/usr/src/uts/sun4u/ml/
H A Dmach_interrupt.s58 * (TT 0x60, TL>0) Interrupt Vector Handler
59 * Globals are the Interrupt Globals.
63 ! Load the interrupt receive data register 0.
65 ! or an interrupt number.
68 ldxa [%g2]ASI_INTR_RECEIVE, %g5 ! %g5 = PC or Interrupt Number
79 bl,a,pt %xcc, 0f ! an interrupt number found
115 ! Load interrupt receive data registers 1 and 2 to fetch
164 ! We have an interrupt number.
189 ! interrupt format
193 ! g5: word 0 of the interrupt data
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/titanic_53/usr/src/uts/common/io/nxge/
H A Dnxge_intr.c55 * Add <channel>'s interrupt.
60 * channel The channel whose interrupt we want to add.
63 * Add here means: add a handler, enable, & arm the interrupt.
75 nxge_intr_t *interrupts; /* The global interrupt data. */ in nxge_intr_add()
117 /* Enable the interrupt. */ in nxge_intr_add()
129 /* Finally, arm the interrupt. */ in nxge_intr_add()
145 * Remove <channel>'s interrupt.
150 * channel The channel whose interrupt we want to remove.
165 nxge_intr_t *interrupts; /* The global interrupt data. */ in nxge_intr_remove()
185 /* Disarm the interrupt. */ in nxge_intr_remove()
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/titanic_53/usr/src/uts/sun4u/io/pci/
H A Dpci_intr.c27 * PCI nexus interrupt handling:
28 * PCI device interrupt handler wrapper
30 * PCI device interrupt related initchild code
49 * interrupt jabber:
51 * When an interrupt line is jabbering, every time the state machine for the
57 * idled when an interrupt line is jabbering. See the comment at the
58 * beginning of pci_intr_wrapper() explaining how the 'interrupt jabber
138 * interrupt handlers of device drivers.
162 "no-dma-interrupt-sync")) in map_pcidev_cfg_reg()
216 * If the unclaimed interrupt count has reached the limit set by
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/titanic_53/usr/src/uts/sun4u/sys/
H A Dmachintreg.h37 * Interrupt Receive Data Registers
54 * Interrupt Receive Status Register
67 * Interrupt Dispatch Data Register
85 * Interrupt Dispatch Command Register
99 * Interrupt Dispatch Command Register
113 * Interrupt Dispatch Status Register
121 #define IDSR_NACK 0x2 /* set if interrupt dispatch failed */
141 * Interrupt Number Register
142 * Every interrupt source has a register associated with it
155 * Starfire interrupt group number is 7 bits
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/titanic_53/usr/src/uts/sun4v/sys/
H A Dcnex.h45 * Channel nexus interrupt map
50 int32_t weight; /* Interrupt weight for device class */
54 * Channel interrupt information
68 /* cnex interrupt types */
70 CNEX_TX_INTR = 1, /* transmit interrupt */
71 CNEX_RX_INTR /* receive interrupt */
84 cnex_intr_t tx; /* Transmit interrupt */
85 cnex_intr_t rx; /* Receive interrupt */
/titanic_53/usr/src/uts/sun4u/serengeti/io/
H A Dsgsbbc.c243 * And get interrupt cookies and initialize the in sbbc_attach()
320 * so the SC can send us interrupt. in sbbc_attach()
399 * us interrupt. in sbbc_detach()
441 * register an interrupt handler in softsp_init()
483 * SBBC Interrupt Handler
485 * Check the SBBC Port Interrupt Status
486 * register to verify that its our interrupt.
489 * Then read the 'interrupt reason' field from SRAM,
520 * our interrupt. However, we don't want to miss the in sbbc_intr_handler()
522 * we always check the interrupt reason bits in IOSRAM in sbbc_intr_handler()
[all …]

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