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/titanic_50/usr/src/uts/common/io/fibre-channel/fca/emlxs/
H A Demlxs_hba.c157 /* Set max interrupt count if not specified */ in emlxs_msi_init()
167 /* Filter max interrupt count with adapter model specification */ in emlxs_msi_init()
172 /* Get the available interrupt types from the kernel */ in emlxs_msi_init()
197 /* Set interrupt type and interrupt count */ in emlxs_msi_init()
203 /* Get the max interrupt count from the adapter */ in emlxs_msi_init()
219 /* Get the max interrupt count from the adapter */ in emlxs_msi_init()
234 /* Get the max interrupt count from the adapter */ in emlxs_msi_init()
266 /* Validate interrupt count */ in emlxs_msi_init()
279 /* Allocate an array of interrupt handles */ in emlxs_msi_init()
321 /* Allocate a new array of interrupt handles */ in emlxs_msi_init()
[all …]
/titanic_50/usr/src/uts/sun4u/serengeti/io/
H A Dsgcn.c82 /* interrupt handlers */
366 /* initialize interrupt handler */ in sgcn_open()
738 * Interrupt handlers
739 * All handlers register with SBBC driver and must follow SBBC interrupt
743 * SC sends an interrupt when new data comes in
754 * change interrupt state so that SBBC won't trigger in sgcn_data_in_handler()
821 * SC sends an interrupt when it takes output data
829 * change interrupt state so that SBBC won't trigger in sgcn_space_2_out_handler()
843 /* restore interrupt state */ in sgcn_space_2_out_handler()
850 * SC sends an interrupt when it detects BREAK sequence
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/titanic_50/usr/src/uts/common/io/ib/adapters/tavor/
H A Dtavor_mr.c87 * Context: Can be called from interrupt or base context.
126 * Context: Can be called from interrupt or base context.
175 * Context: Can be called from interrupt or base context.
199 * current thread context (i.e. if we are currently in the interrupt in tavor_mr_register_shared()
472 * Context: Can be called from interrupt or base context.
492 * current thread context (i.e. if we are currently in the interrupt in tavor_mr_deregister()
661 * Context: Can be called from interrupt or base context.
723 * Context: Can be called from interrupt or base context.
763 * Context: Can be called from interrupt or base context.
812 * Context: Can be called from interrupt or base context.
[all …]
/titanic_50/usr/src/uts/common/io/ib/adapters/hermon/
H A Dhermon_mr.c100 * Context: Can be called from interrupt or base context.
131 * Context: Can be called from interrupt or base context.
170 * Context: Can be called from interrupt or base context.
190 * current thread context (i.e. if we are currently in the interrupt in hermon_mr_register_shared()
440 * Context: Can be called from interrupt or base context.
461 * current thread context (i.e. if we are currently in the interrupt in hermon_mr_alloc_fmr()
652 * Context: Can be called from interrupt or base context.
741 * Context: Can be called from interrupt or base context.
759 * current thread context (i.e. if we are currently in the interrupt in hermon_mr_deregister()
938 * Context: Can be called from interrupt or base context.
[all …]
/titanic_50/usr/src/uts/common/disp/
H A Dthread.c544 * The interrupt routine must set the thread dispatcher in thread_create()
868 * <interrupt> in thread_zone_destroy()
874 * A cross call to all cpus will cause the interrupt handler in thread_zone_destroy()
930 * <interrupt> in thread_reaper()
936 * A cross call to all cpus will cause the interrupt handler in thread_reaper()
1300 * When an interrupt occurs, the interrupt is handled on the stack
1301 * of an interrupt thread, taken from a pool linked to the CPU structure.
1303 * When swtch() is switching away from an interrupt thread because it
1315 int i; /* interrupt level */ in thread_unpin()
1321 t->t_intr = NULL; /* clear interrupt ptr */ in thread_unpin()
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/titanic_50/usr/src/uts/sun4/ml/
H A Dswtch.s411 ! Set priority as low as possible, blocking all interrupt threads
419 ! If we are resuming an interrupt thread, store a starting timestamp
441 ! If an interrupt occurred while we were attempting to store
532 ! switching out of the interrupt context.
573 ! If we are resuming an interrupt thread, store a timestamp in the
580 ! We're resuming a non-interrupt thread.
591 ! We're an interrupt thread. Update t_intr_start and cpu_intrcnt
609 ! We're a non-interrupt thread and cpu_kprunrun is set. call kpreempt.
/titanic_50/usr/src/uts/sparc/v9/ml/
H A Dsyscall_trap.s110 wrpr %g0, %g3, %pstate ! disable interrupt
128 wrpr %g0, %l3, %pstate ! enable interrupt
193 wrpr %g0, %g4, %pstate ! disable interrupt
213 wrpr %g0, %g5, %pstate ! enable interrupt
355 wrpr %g0, %g3, %pstate ! disable interrupt
373 wrpr %g0, %l3, %pstate ! enable interrupt
451 wrpr %g0, %g4, %pstate ! disable interrupt
471 wrpr %g0, %g5, %pstate ! enable interrupt
/titanic_50/usr/src/uts/intel/io/drm/
H A Di915_irq.c94 /* For display hotplug interrupt */
154 /* Enable the interrupt, clear any pending status */ in i915_enable_pipestat()
232 * interrupt) to capture error state from the time of the error. Fills
295 * i915_handle_error - handle an error interrupt
298 * Do some basic checking of regsiter state at error interrupt time and
437 /* disable master interrupt before clearing iir */ in igdng_irq_handler()
524 /* The vblank interrupt gets enabled even if we didn't ask for in i915_driver_irq_handler()
541 /* The vblank interrupt gets enabled even if we didn't ask for in i915_driver_irq_handler()
926 /* user interrupt should be enabled, but masked initial */ in igdng_irq_postinstall()
1009 /* Disable pipe interrupt enables, clear pending pipe status */ in i915_driver_irq_postinstall()
[all …]
/titanic_50/usr/src/uts/common/sys/usb/hcd/openhci/
H A Dohci_polled.h64 * For ohci bandwidth of low speed interrupt devices limits,
87 /* Interrupt Endpoint descriptor */
88 ohci_ed_t *ohci_polled_ed; /* Interrupt endpoint */
/titanic_50/usr/src/uts/common/io/ntxn/
H A Dnx_hw_pci_regs.h39 * Interrupt related defines.
79 * Interrupt state machine and other bits.
113 * PCI Interrupt Vector Values.
/titanic_50/usr/src/uts/sun4u/sys/
H A Drmc_comm_drvintf.h63 #define RCECANTREGINTR (-9) /* interrupt handler registration failure */
64 #define RCEALREADYREG (-10) /* interrupt handler already registered */
72 * interrupt handler is currently processing an asynchronous notification or
H A Dsysioerr.h37 * Sbus error interrupt priorities
52 #define SYSIO_INTGN 0x0007C00000000000ULL /* interrupt group number */
62 #define SECR_UE_INTEN 0x4000000000000000ULL /* enable UE_INT interrupt */
63 #define SECR_CE_INTEN 0x2000000000000000ULL /* enable CE_INT interrupt */
/titanic_50/usr/src/uts/sun4u/sys/pci/
H A Dpci_pbm.h106 * pbm Interrupt Mapping Register save area
110 /* To save CDMA interrupt state across CPR */
114 * pbm error interrupt priority:
H A Dpci_var.h135 ib_t *pci_ib_p; /* interrupt block */
156 int pci_numproxy; /* upa interrupt proxies */
157 int pci_thermal_interrupt; /* node has thermal interrupt */
165 /* Interrupt support */
/titanic_50/usr/src/uts/common/io/rge/
H A Drge_chip.c381 * is complete. We should get a link state change interrupt somewhere along
849 * Disable interrupt in rge_chip_reset()
855 * Clear pended interrupt in rge_chip_reset()
1070 * Enable interrupt in rge_chip_start()
1100 * Disable interrupt in rge_chip_stop()
1106 * Clear pended interrupt in rge_chip_stop()
1333 * ========== Hardware interrupt handler ==========
1381 * Was this interrupt caused by our device... in rge_intr()
1387 /* indicate it wasn't our interrupt */ in rge_intr()
1392 * Clear interrupt in rge_intr()
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/titanic_50/usr/src/uts/sun4u/sunfire/io/
H A Dfhc.c84 * This table represents the FHC interrupt priorities. They range from
90 PIL_15, /* System interrupt priority */
91 PIL_12, /* zs interrupt priority */
92 PIL_15, /* TOD interrupt priority */
348 /* Interrupt distribution callback function. */
502 * Reset the interrupt mapping registers.
515 * have to have to tear down and rebuild the interrupt records
560 /* Loop through all 4 FHC interrupt mapping registers */ in fhc_handle_imr()
566 "found lost system interrupt, resetting.."); in fhc_handle_imr()
632 /* reset interrupt mapping registers */ in fhc_attach()
[all …]
/titanic_50/usr/src/man/man9f/
H A Dusb_pipe_isoc_xfer.9f151 since they are called from interrupt context. They will have
256 Called from interrupt context with the USB_FLAGS_SLEEP flag set.
372 None, but will fail if called with USB_FLAGS_SLEEP specified from interrupt
380 regard to arguments. May be called from interrupt context only when the
/titanic_50/usr/src/uts/common/sys/
H A Ddditypes.h102 * Interrupt types
117 uint_t idev_softint; /* Soft interrupt register bit(s) */
128 * interrupt specification
135 * soft interrupt id
/titanic_50/usr/src/uts/common/io/usb/usba/
H A DREADME170 3. Interrupt pipe state transitions (endpoint number > 1, both IN and OUT) :-
172 Interrupt IN:
207 Interrupt OUT:
209 NOTE: Send all interrupt OUT requests to HCD and no queuing at USBA level.
/titanic_50/usr/src/uts/intel/ia32/ml/
H A Dswtch.s138 * If we are resuming an interrupt thread, store a timestamp in the thread
139 * structure. If an interrupt occurs between tsc_read() and its subsequent
142 * interrupt occurring in this window will put a new timestamp in the thread's
200 * If we are resuming an interrupt thread, store a timestamp in the thread
201 * structure. If an interrupt occurs between tsc_read() and its subsequent
204 * interrupt occurring in this window will put a new timestamp in the thread's
392 * possible and blocking all interrupt threads that may be active.
560 * possible and blocking all interrupt threads that may be active.
790 * possible and blocking all interrupt threads that may be active.
840 * possible and blocking all interrupt threads that may be active.
/titanic_50/usr/src/uts/sun4/os/
H A Dmachdep.c430 * Create interrupt kstats for this CPU.
472 * Delete interrupt kstats for this CPU.
481 * Convert interrupt statistics from CPU ticks to nanoseconds and
524 * An interrupt thread is ending a time slice, so compute the interval it
539 * an interrupt thread which no longer has a pinned thread underneath in cpu_intr_swtch_enter()
541 * its handler. intr_thread() updated the interrupt statistic for its in cpu_intr_swtch_enter()
545 * It can also happen if an interrupt thread in intr_thread() calls in cpu_intr_swtch_enter()
547 * this event, the interrupt thread will be runnable. in cpu_intr_swtch_enter()
567 * An interrupt thread is returning from swtch(). Place a starting timestamp
878 * We need to post a soft interrupt to reprogram the lbolt cyclic when
/titanic_50/usr/src/cmd/cpc/common/
H A Dcputrack.c67 * We bail out as soon as possible when interrupt is set
69 static int interrupt = 0; variable
334 if (interrupt) in pinit_lwp()
400 if (interrupt) in pfini_lwp()
454 if (interrupt) in plwp_create()
475 if (interrupt) in plwp_exit()
501 if (interrupt) in pexec()
544 if (interrupt) in pexit()
581 if (interrupt) in ptick()
883 interrupt++; in intr()
/titanic_50/usr/src/uts/common/os/
H A Dkcpc.c68 static uint32_t kcpc_intrctx_count; /* # overflows in an interrupt handler */
98 * cross-call or from high-PIL interrupt
913 * Generic interrupt handler used on hardware that generates
916 * Note: executed at high-level interrupt context!
928 * interrupt in kernel mode, just after we've started to run an in kcpc_overflow_intr()
929 * interrupt thread. (That's because the hardware helpfully in kcpc_overflow_intr()
930 * delivers the overflow interrupt some random number of cycles in kcpc_overflow_intr()
936 * that was running when the interrupt went off. in kcpc_overflow_intr()
959 * "shared" mode, for example, and an overflow interrupt in kcpc_overflow_intr()
970 * the interrupt handler so that it can synchronously in kcpc_overflow_intr()
[all …]
/titanic_50/usr/src/man/man9s/
H A Dusb_request_attributes.9s88 Applies only to interrupt-IN requests. Without this flag, interrupt-IN requests
89 start periodic polling of the interrupt pipe. This flag specifies to perform
/titanic_50/usr/src/uts/common/io/fibre-channel/fca/qlc/
H A Dql_iocb.c69 * Interrupt or Kernel context, no mailbox commands allowed.
266 * Interrupt or Kernel context, no mailbox commands allowed.
331 * XXX protect interrupt routine from calling itself. in ql_req_pkt()
366 * Interrupt or Kernel context, no mailbox commands allowed.
424 * Interrupt or Kernel context, no mailbox commands allowed.
544 * Interrupt or Kernel context, no mailbox commands allowed.
636 * Interrupt or Kernel context, no mailbox commands allowed.
767 * Interrupt or Kernel context, no mailbox commands allowed.
912 * Interrupt or Kernel context, no mailbox commands allowed.
980 * Interrupt or Kernel context, no mailbox commands allowed.
[all …]

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