| /titanic_51/usr/src/boot/sys/boot/fdt/dts/arm/ |
| H A D | armada-388-gp.dts | 94 interrupt-parent = <&gpio0>;
98 interrupt-controller;
99 #interrupt-cells = <2>;
106 interrupt-parent = <&gpio0>;
110 interrupt-controller;
111 #interrupt-cells = <2>;
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| /titanic_51/usr/src/man/man9f/ |
| H A D | usb_pipe_get_state.9f | 77 interrupt pipes.
86 Polling is stopped for isochronous and interrupt-IN pipes.
141 May be called from user, kernel or interrupt context.
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| H A D | ddi_get8.9f | 80 high-interrupt context. These types include \fBISA\fR and SBus buses. See
83 high-interrupt context. See \fBpci\fR(4).
91 These functions can be called from user, kernel, or interrupt context.
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| H A D | ddi_put8.9f | 94 high-interrupt context. These types include \fBISA\fR and SBus buses. See
97 high-interrupt context. See \fBpci\fR(4).
101 These functions can be called from user, kernel, or interrupt context.
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| H A D | id32_alloc.9f | 92 These functions can be called from user or interrupt context. The routine
93 \fBid32_alloc()\fR should not be called from interrupt context when the
95 interrupt or kernel context.
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| H A D | scsi_hba_pkt_alloc.9f | 212 The \fBscsi_hba_pkt_alloc()\fR function can be called from user, interrupt, or
214 called from an interrupt routine.
217 The \fBscsi_hba_pkt_free()\fR function can be called from user, interrupt, or
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| /titanic_51/usr/src/uts/common/io/chxge/com/ |
| H A D | fpga_defs.h | 38 /* FPGA master interrupt Cause/Enable bits */
46 /* TP interrupt register addresses */
51 /* TP interrupt Cause/Enable bits */
56 * PM interrupt register addresses
63 * GMAC interrupt register addresses
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| H A D | pm3393.c | 118 2. Enable PM3393 Master Interrupt bit(INTE)
120 4. Enable Terminator external interrupt.
136 /* Don't interrupt on statistics overflow, we are polling */ in pm3393_interrupt_enable()
152 /* PM3393 - Global interrupt enable in pm3393_interrupt_enable()
177 /* PM3393 - Enabling HW interrupt blocks. */ in pm3393_interrupt_disable()
196 /* PM3393 - Global interrupt enable */ in pm3393_interrupt_disable()
218 /* PM3393 - Clearing HW interrupt blocks. Note, this assumes in pm3393_interrupt_clear()
237 /* PM3393 - Global interrupt status in pm3393_interrupt_clear()
256 /* Interrupt handler */
261 1. Read master interrupt registe in pm3393_interrupt_handler()
[all...] |
| /titanic_51/usr/src/uts/sun4u/starfire/io/ |
| H A D | portctrl.c | 37 * Interrupt target translation data for
48 * represent the Starfire interrupt target translation
63 * interrupt target translations in pc_ittrans_init()
82 * This soft table is used to represent the interrupt in pc_ittrans_init()
172 * This routine searches the interrupt target translation table
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| /titanic_51/usr/src/uts/sun4u/io/pci/ |
| H A D | pci_cb.c | 85 * enable an internal interrupt source:
86 * if an interrupt is shared by both sides, record it in cb_inos[] and
130 /* mark interrupt invalid in mapping register */ in cb_disable_nintr_reg()
140 /* busy wait if there is interrupt being processed */ in cb_disable_nintr_reg()
141 /* unless panic or timeout for interrupt pending is reached */ in cb_disable_nintr_reg()
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| /titanic_51/usr/src/uts/common/sys/1394/adapters/ |
| H A D | hci1394_isoch.h | 81 kmutex_t intrprocmutex; /* interrupt/update coordination */
82 kcondvar_t intr_cv; /* interrupt completion cv */
153 * structure used to do accounting for interrupt usage. Specifically,
173 * CYCLE_INCONSISTENT interrupt usage.
176 * during interrupt processing, and during free_isoch_dma processing.
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| /titanic_51/usr/src/uts/common/io/sata/adapters/si3124/ |
| H A D | si3124.c | 100 * the interrupt. By comparing the slot_status register contents with
515 * the interrupt handlers and then register ourselves with sata framework.
617 * Disable all the interrupts before adding interrupt in si_attach()
623 /* Get supported interrupt types. */ in si_attach()
637 "Using MSI interrupt type", NULL); in si_attach()
647 "MSI interrupt setup done", NULL); in si_attach()
658 * Either the MSI interrupt setup has failed or only in si_attach()
662 "Using Legacy interrupt type", NULL); in si_attach()
668 "Legacy interrupt setup done", NULL); in si_attach()
671 "legacy interrupt setu in si_attach()
[all...] |
| /titanic_51/usr/src/boot/sys/boot/fdt/dts/mips/ |
| H A D | xlp-basic.dts | 52 interrupt-controller;
54 #interrupt-cells = <1>;
64 interrupt-parent = <&pic>;
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| /titanic_51/usr/src/uts/common/io/yge/ |
| H A D | yge.h | 259 #define B0_ISRC 0x0008 /* 32 bit Interrupt Source Register */
260 #define B0_IMSK 0x000c /* 32 bit Interrupt Mask Register */
261 #define B0_HWE_ISRC 0x0010 /* 32 bit HW Error Interrupt Src Reg */
262 #define B0_HWE_IMSK 0x0014 /* 32 bit HW Error Interrupt Mask Reg */
263 #define B0_SP_ISRC 0x0018 /* 32 bit Special Interrupt Source Reg 1 */
266 #define B0_Y2_SP_ISRC2 0x001c /* 32 bit Special Interrupt Source Reg 2 */
267 #define B0_Y2_SP_ISRC3 0x0020 /* 32 bit Special Interrupt Source Reg 3 */
270 #define B0_Y2_SP_ICR 0x002c /* 32 bit Interrupt Control Reg */
567 #define GMAC_IRQ_SRC 0x0f08 /* 8 bit GMAC Interrupt Source Reg */
568 #define GMAC_IRQ_MSK 0x0f0c /* 8 bit GMAC Interrupt Mas
[all...] |
| /titanic_51/usr/src/uts/common/io/fibre-channel/fca/qlge/ |
| H A D | qlge_mpi.c | 31 * Wait upto timeout seconds for Processor Interrupt
41 cmn_err(CE_WARN, "Polling for processor interrupt failed."); in ql_poll_processor_intr()
223 * interrupt is not enabled.
245 max_wait = 5; /* wait upto 5 PI interrupt */ in ql_issue_mailbox_cmd_and_poll_rsp()
246 /* delay for the processor interrupt is received */ in ql_issue_mailbox_cmd_and_poll_rsp()
248 /* wait up to 5s for PI interrupt */ in ql_issue_mailbox_cmd_and_poll_rsp()
260 * PI interrupt in ql_issue_mailbox_cmd_and_poll_rsp()
265 * clear the interrupt in ql_issue_mailbox_cmd_and_poll_rsp()
288 * is saved in interrupt. Thus, this function can only
289 * be used after interrupt i
[all...] |
| /titanic_51/usr/src/uts/common/io/ib/adapters/hermon/ |
| H A D | hermon_rsrc.c | 175 * Context: Can be called from interrupt or base context.
536 * Context: Can be called from interrupt or base context.
700 /* Initialize the resource pool for "interrupt out" mailboxes */ in hermon_rsrc_init_phase1()
760 /* Initialize the resource pool for "interrupt in" mailboxes */ in hermon_rsrc_init_phase1()
1428 /* Cleanup the interrupt "In" mailbox resource pool */ in hermon_rsrc_fini()
1446 /* Cleanup the interrupt "Out" mailbox list */ in hermon_rsrc_fini()
1875 * Context: Can be called from interrupt or base context.
1892 * Context: Can be called from interrupt or base context.
1954 * Context: Can be called from interrupt or base context.
2002 * Context: Can be called from interrupt o
[all...] |
| /titanic_51/usr/src/uts/common/io/ib/adapters/tavor/ |
| H A D | tavor_wr.c | 93 * Context: Can be called from interrupt or base context.
393 * Context: Can be called from interrupt or base context.
648 * Context: Can be called from interrupt or base context.
889 * Context: Can be called from interrupt or base context.
915 * Context: Can be called from interrupt or base context.
940 * Context: Can be called from interrupt or base context.
1301 * Context: Can be called from interrupt or base context.
1430 * Context: Can be called from interrupt or base context.
1670 * Context: Can be called from interrupt or base context.
1801 * Context: Can be called from interrupt o
[all...] |
| /titanic_51/usr/src/uts/i86pc/io/pcplusmp/ |
| H A D | apic.c | 34 * To understand how the pcplusmp module interacts with the interrupt subsystem
149 * to the IPLs in apic_vectortoipl on some systems that share interrupt lines
158 int apic_enable_bind_log = 1; /* 1 - display interrupt binding log */
201 apic_intr_ops, /* Advanced DDI Interrupt framework */
333 * Setting the 12th bit in the Spurious Interrupt Vector in apic_init_intr()
346 * cause an error interrupt, even if the entry is masked...so in apic_init_intr()
369 /* Enable performance counter overflow interrupt */ in apic_init_intr()
407 /* Enable error interrupt */ in apic_init_intr()
430 /* Enable CMCI interrupt */ in apic_init_intr()
465 * Initialize and enable interrupt remappin in apic_picinit()
[all...] |
| /titanic_51/usr/src/uts/common/io/ |
| H A D | pci_intr_lib.c | 62 * after x86 interrupt scalability support.
81 * NICs some isolation from other interrupt sources. We need better interfaces
84 * NICs additional isolation from other interrupt sources.
152 * Get the capabilities of the MSI/X interrupt
393 * interrupt's mask bit in the MSI/X capability structure before the
394 * interrupt can be used.
441 * interrupt's mask bit in the MSI/X capability structure before the
442 * interrupt can be disabled.
996 * Next set of routines are for INTx (legacy) PCI interrupt
1003 * read the command register. Bit 10 implies interrupt disabl
[all...] |
| /titanic_51/usr/src/uts/common/dtrace/ |
| H A D | dcpc.c | 53 * interrupt will be generated and the probe is fired.
62 * overflow interrupt. In this case we cannot reliably determine which counter
69 * overflow interrupt are only allowed to program a single event at one time.
124 * Called from the platform overflow interrupt handler. 'bitmap' is a mask
553 * per-CPU dcpc interrupt state byte. The purpose of the state byte is to
557 * The dcpc provider claims ownership of the overflow interrupt mechanism
564 * an interrupt when a configuration is not in process (i.e. the state is
565 * marked as free). During interrupt processing the state is set to
589 * Set all CPUs dcpc interrupt state to DCPC_INTR_FREE to indicate that
606 * Transition all CPUs dcpc interrupt stat
[all...] |
| /titanic_51/usr/src/uts/sun4u/io/i2c/nexus/ |
| H A D | smbus.c | 162 * The "interrupt-priorities" property is how a driver can specify a SPARC
163 * PIL level to associate with each of its interrupt properties. Most
300 "interrupt-priorities"); in smbus_dodetach()
358 * The "interrupt-priorities" property is how a driver can in smbus_doattach()
360 * interrupt properties. Most self-identifying busses have in smbus_doattach()
365 "interrupt-priorities") != 1) { in smbus_doattach()
367 DDI_PROP_CANSLEEP, "interrupt-priorities", in smbus_doattach()
374 * Clear status to clear any possible interrupt in smbus_doattach()
385 cmn_err(CE_WARN, "%s failed to add interrupt", in smbus_doattach()
960 * If timeout is already cleared, it means interrupt arrive in smbus_intr_timeout()
[all...] |
| /titanic_51/usr/src/boot/sys/boot/fdt/dts/ |
| H A D | bindings-gpio.txt | 45 interrupt-parent = <&PIC>;
86 0x0002---- IN_IRQ_EDGE Interrupt, edge triggered.
87 0x0004---- IN_IRQ_LEVEL Interrupt, level triggered.
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| /titanic_51/usr/src/uts/intel/io/amd8111s/ |
| H A D | amd8111s_hw.c | 104 /* Set Interrupt Delay Parameters */ in mdlInitGlbds()
432 * Read the NIC interrupt.
435 * the value of interrupt causes register
446 * INT0 identifies the source or sources of an interrupt. With the in mdlReadInterrupt()
448 * 1 to clear" so that the CPU can clear the interrupt condition by in mdlReadInterrupt()
453 /* Read interrupt status */ in mdlReadInterrupt()
540 /* Enable Following Interrupt */ in mdlHWReset()
803 /* Enable Interrupt and Start processing descriptor, Rx and Tx */ in mdlStartChip()
819 /* Disable interrupt */ in mdlStopChip()
822 /* Clear interrupt statu in mdlStopChip()
[all...] |
| /titanic_51/usr/src/uts/common/io/1394/adapters/ |
| H A D | hci1394_ixl_update.c | 55 * interrupt routine to complete.
103 * simultaneous run of interrupt stack, evaluates likelyhood of success,
105 * resulting from coordination with interrupt stack.
170 /* perform update processing reservation of interrupt context */ in hci1394_ixl_update()
194 * error is dmalost, just release interrupt context. in hci1394_ixl_update()
198 * interrupt routine. in hci1394_ixl_update()
216 * attempt interrupt processing cleanup first in hci1394_ixl_update()
230 * update failed - bad, just release interrupt context in hci1394_ixl_update()
234 * from the interrupt routine. in hci1394_ixl_update()
256 /* perform interrupt processin in hci1394_ixl_update()
[all...] |
| /titanic_51/usr/src/uts/i86pc/io/amd_iommu/ |
| H A D | amd_iommu_log.c | 95 "Posted write to Interrupt/EOI Range " in get_illegal_req()
100 "Posted write to reserved Interrupt Address Range"; in get_illegal_req()
160 I == 1 ? "Interrupt" : "Memory", in devtab_illegal_entry()
215 PR == 1 ? "Page present or Interrupt Remapped" : in io_page_fault()
216 "Page not present or Interrupt Blocked", in io_page_fault()
217 I == 1 ? "Interrupt" : "Memory", in io_page_fault()
266 I == 1 ? "Interrupt" : "Memory", in devtab_hw_error()
319 I == 1 ? "Interrupt" : "Memory", in pgtable_hw_error()
|