| /titanic_53/usr/src/uts/common/io/hxge/ |
| H A D | hxge_pfc_hw.h | 526 * PFC Interrupt Status
527 * Description: PFC interrupt status register
557 * PFC Debug Interrupt Status
558 * Description: PFC debug interrupt status mirror register. This
560 * Interrupt Status register. Interrupts in this mirror register are
561 * subject to the filtering of the PFC Interrupt Mask register.
589 * PFC Interrupt Mask
590 * Description: PFC interrupt status mask register
620 * is re-armed when associated interrupt bit is cleared.
696 * interrupt bit is cleared by writing '1'.
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| /titanic_53/usr/src/uts/common/io/sata/adapters/nv_sata/ |
| H A D | nv_sata.c | 328 * single invocation of the port interrupt routine.
680 * get supported interrupt types in nv_attach()
697 "using MSI interrupt type", NULL); in nv_attach()
707 "MSI interrupt setup done", NULL); in nv_attach()
717 * Either the MSI interrupt setup has failed or only in nv_attach()
724 "using Legacy interrupt type", NULL); in nv_attach()
730 "Legacy interrupt setup done", NULL); in nv_attach()
733 "legacy interrupt setup failed"); in nv_attach()
735 "legacy interrupt setup failed", NULL); in nv_attach()
1562 * if SYNC but not POLL, verify that this is not on interrupt thread. in nv_start_sync()
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| /titanic_53/usr/src/uts/sun4/os/ |
| H A D | x_call.c | 47 static uint64_t xc_serv_inum; /* software interrupt number for xc_serv() */
48 static uint64_t xc_loop_inum; /* software interrupt number for xc_loop() */
169 * inter-processor interrupt services:
201 * func - a TL>0 handler address or an interrupt number
204 * 0 when "func" is an interrupt number
214 * to be an assigned interrupt number through add_softintr().
215 * An interrupt number is an index to the interrupt vector table,
216 * which entry contains an interrupt handler address with its
217 * corresponding interrupt level and argument.
260 * dmv interrupt in xt_one_unchecked()
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| /titanic_53/usr/src/uts/sun4u/io/ |
| H A D | rmc_comm.c | 199 * instructions - including exiting the interrupt service in sio_put_reg()
276 * High-level interrupt handler:
279 * If not, the interrupt's not for us, so just return UNCLAIMED.
280 * Otherwise, disable the interrupt, trigger a softint, and return
283 * NOTE: the chip interrupt capability is only re-enabled once the
286 * guaranteed that there really is a chip interrupt pending here,
288 * interrupt gone away before we get here.
305 * Handle the case where this interrupt fires during in rmc_comm_hi_intr()
608 * the interrupt block cookie so that the mutexes are initialized in rmc_comm_serdev_init()
609 * before adding the interrupt (to avoid a potential race condition). in rmc_comm_serdev_init()
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| /titanic_53/usr/src/uts/common/os/ |
| H A D | ddi_intr_irm.c | 45 * Interrupt Resource Management (IRM).
64 /* Global list of interrupt pools */
104 /* Initialize the global list of interrupt pools */ in irm_init()
152 * pool and add it to the global list of interrupt pools.
295 * and remove it from the global list of interrupt pools.
342 * Insert/Modify/Remove Interrupt Requests
348 * Insert a new request into an interrupt pool, and balance the pool.
408 cmn_err(CE_WARN, "%s%d: interrupt pool too full.\n", in i_ddi_irm_insert()
461 cmn_err(CE_WARN, "%s%d: interrupt pool too full.\n", in i_ddi_irm_insert()
481 * Modify an existing request in an interrupt pool, and balance the pool.
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| /titanic_53/usr/src/uts/sun4/sys/ |
| H A D | ebus.h | 45 * deal with differences in the interrupt dispatching between the prototypes
46 * and the cheerio ebus. On the prototype boards, all interrupt lines are
47 * tied together. For this case, the nexus driver uses a common interrupt
54 * ebus device interrupt info;
141 /* Interrupt support */
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| /titanic_53/usr/src/man/man3curses/ |
| H A D | curs_inopts.3curses | 109 Interrupt and flow control characters are unaffected by this mode. Initially
140 interrupt key is pressed on the keyboard (interrupt, break, quit) all output in
142 the interrupt, but causing \fBcurses\fR to have the wrong idea of what is on
184 that in raw mode, the interrupt, quit, suspend, and flow control characters are
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| /titanic_53/usr/src/uts/common/io/ib/adapters/hermon/ |
| H A D | hermon_event.c | 28 * Hermon Interrupt and Event Processing Routines
33 * These routines include the main Hermon interrupt service routine
102 * same interrupt or MSI. In the future we may support assigning in hermon_eq_init_all()
434 * Context: Only called from interrupt context (and during panic)
448 /* Get the interrupt number */ in hermon_isr()
452 * Clear the interrupt. Note: This is only needed for in hermon_isr()
482 * events, whereas the "if" case deals with the required interrupt in hermon_isr()
506 * Context: Only called from interrupt context (and during panic)
611 * Context: Only called from interrupt context (and during panic)
820 * "fired" state. We will arm them later (after our interrupt in hermon_eq_alloc()
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| /titanic_53/usr/src/uts/sun4/io/px/ |
| H A D | px_pec.c | 29 * Bus error interrupt handler
140 * Add interrupt handlers to process correctable/fatal/non fatal
179 "PCIE_CORR_MSG update interrupt state failed\n"); in px_pec_msg_add_intr()
203 "PCIE_NONFATAL_MSG update interrupt state failed\n"); in px_pec_msg_add_intr()
225 "PCIE_FATAL_MSG update interrupt state failed\n"); in px_pec_msg_add_intr()
235 * Remove interrupt handlers to process correctable/fatal/non fatal
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| /titanic_53/usr/src/uts/sun4u/os/ |
| H A D | mach_ddi_impl.c | 195 * Routines to set/get UPA slave only device interrupt mapping registers.
197 * of an interrupt mapping register. The upa id is that of the master. If
202 * of a child device to get and program the interrupt mapping register of
251 * We only get here if we're a UPA slave only device whose interrupt in get_intr_mapping_reg()
260 * We don't know if a single- or multi-interrupt proxy is fielding in get_intr_mapping_reg()
261 * our UPA slave interrupt, we must check both cases. in get_intr_mapping_reg()
262 * Start out by assuming the multi-interrupt case. in get_intr_mapping_reg()
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| /titanic_53/usr/src/uts/sun/io/eri/ |
| H A D | eri_mac.h | 79 #define ERI_TMD_INTME ((uint64_t)1 << 32) /* 32 : Interrupt me now */
168 uint32_t intmask; /* 0x0010 RW 0xFFFFFFFF 12 Interrupt Mask Reg */
169 uint32_t intack; /* 0x0014 WO 0x00000000 06 Interrupt Ack Register */
214 * Global Interrupt Status Register (R-AC)
234 #define ERI_G_STATUS_PCS_INT (1 << 13) /* 13 - PCS Interrupt */
261 * Global Interrupt Mask register (RW)
266 * If a mask bit is 0, the corresponding event causes an interrupt.
279 #define ERI_G_MASK_PCS_INT (1 << 13) /* 13 - PCS Interrupt */
291 * Interrupt Ack Register (WO)
292 * Its layout corresponds to the layout of the top level bits of the Interrupt
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| /titanic_53/usr/src/uts/common/io/ib/adapters/tavor/ |
| H A D | tavor_event.c | 29 * Tavor Interrupt and Event Processing Routines
34 * These routines include the main Tavor interrupt service routine
101 * same interrupt or MSI. In the future we may support assigning in tavor_eq_init_all()
109 * MSI enable flag. Otherwise, for regular (i.e. 'legacy') interrupt, in tavor_eq_init_all()
360 * occurs. Instead, an interrupt is called and we must poll the in tavor_eq_init_all()
555 * Context: Only called from interrupt context (and during panic)
590 * fired EQ. If no ECR bits are set, do not claim the interrupt. in tavor_isr()
605 * Clear the interrupt. Note: Depending on the type of in tavor_isr()
606 * event (interrupt or MSI), we need to use a different in tavor_isr()
630 * Context: Only called from interrupt context
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| /titanic_53/usr/src/uts/common/io/sfe/ |
| H A D | sfereg.h | 125 #define ISR 0x10 /* Interrupt status register */
126 #define IMR 0x14 /* Interrupt mask register */
127 #define IER 0x18 /* Interrupt enable register */
150 #define CR_SWI 0x0080U /* Software interrupt */
176 #define CFG_PINT_ACEN 0x00020000U /* PHY interrupt auto clear (83815) */
246 /* Interrupt status register */
298 /* Interrupt enable reigster */
299 #define IER_IE 0x00000001 /* Interrupt enable */
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| /titanic_53/usr/src/uts/sun4v/io/ |
| H A D | vnex.c | 60 /* vnex interrupt descriptor */
73 /* vnex interrupt descriptor list */
79 * vnex interrupt descriptor list manipulation functions
187 * This driver uses the old interrupt routines which are supported in _init()
268 * Intitialize interrupt descriptor list in vnex_attach()
274 * Add interrupt redistribution callback. in vnex_attach()
493 * Allocate a interrupt descriptor (id) with the in vnex_add_intr()
494 * the interrupt handler and append it to in vnex_add_intr()
642 cmn_err(CE_PANIC, "vnex: interrupt list empty"); in vnex_rem_id()
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| /titanic_53/usr/src/uts/common/io/usb/scsa2usb/ |
| H A D | usb_ms_cbi.c | 30 * Control Bulk Interrupt (CB/CBI) transport v1.0
123 * Status Phase: (on Interrupt pipe for CBI devices only)
127 * clear stall on interrupt pipe
254 /* CB devices don't do status over interrupt pipe */ in scsa2usb_cbi_transport()
265 /* Get Status over interrupt pipe */ in scsa2usb_cbi_transport()
275 /* stop interrupt pipe polling (CBI only) */ in scsa2usb_cbi_transport()
406 * Stop polling on interrupt pipe (for status)
476 /* non-zero command completion interrupt */ in scsa2usb_handle_cbi_status()
585 /* reset and clear STALL on interrupt pipe */ in scsa2usb_cbi_reset_recovery()
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| /titanic_53/usr/src/uts/sun4u/sunfire/io/ |
| H A D | sysctrl.c | 227 * (used both for interrupt retry timeout and polling function)
231 /* # of ticks delay after board insert interrupt */
249 /* Specify which system interrupt condition to monitor */
565 /* shut off all interrupt sources */ in sysctrl_attach()
574 * Now register our high interrupt with the system. in sysctrl_attach()
664 * not enable the board insert interrupt for this session. in sysctrl_attach()
708 * Now register led blink handler (interrupt level) in sysctrl_attach()
730 /* Now enable selected interrupt sources */ in sysctrl_attach()
1432 * This routine goes through all the interrupt sources and masks
1462 /* disable this interrupt source */ in system_high_handler()
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| /titanic_53/usr/src/man/man9f/ |
| H A D | scsi_poll.9f | 67 The \fBscsi_poll()\fR function can be called from user, interrupt, or kernel
81 require more time than is desirable when called from interrupt context.
82 Therefore, calling \fBscsi_poll\fR from interrupt context is not recommended.
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| H A D | ddi_log_sysevent.9f | 185 \fIsleep_flag\fR is DDI_SLEEP and the driver is running in interrupt context.
254 The \fBddi_log_sysevent()\fR function can be called from user, interrupt, or
256 it cannot be called from interrupt context.
300 needing to generate an event from interrupt context.
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| /titanic_53/usr/src/uts/sun4/io/ |
| H A D | su_driver.c | 101 /* The async interrupt entry points */
642 "Get iblock_cookie failed-Device interrupt%x\n", instance); in asyattach()
648 cmn_err(CE_NOTE, "Get iblock_cookie failed -soft interrupt%x\n", in asyattach()
661 * Install interrupt handlers for this device. in asyattach()
666 "Cannot set device interrupt for su driver\n"); in asyattach()
674 cmn_err(CE_CONT, "Cannot set soft interrupt for su driver\n"); in asyattach()
1027 * Quit on interrupt. in asyopen()
1074 * having had at least one transmitter interrupt. If none of these are in async_progress_check()
1187 * the interrupt routine grabs buffers from the write queue, we can't in asyclose()
1233 /* turn off DTR, RTS but NOT interrupt to 386 */ in asyclose()
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| /titanic_53/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/ |
| H A D | bnxe_hw_debug.c | 662 …IDLE_CHK_1(0x1F, CFC_REG_CFC_INT_STS, (val != 0), IDLE_CHK_ERROR, "CFC: Interrupt status is not 0"… in lm_idle_chk()
664 …IDLE_CHK_1(0x1F, CDU_REG_CDU_INT_STS, (val != 0), IDLE_CHK_ERROR, "CDU: Interrupt status is not 0"… in lm_idle_chk()
666 …IDLE_CHK_1(0x1F, CCM_REG_CCM_INT_STS, (val != 0), IDLE_CHK_ERROR, "CCM: Interrupt status is not 0"… in lm_idle_chk()
668 …IDLE_CHK_1(0x1F, TCM_REG_TCM_INT_STS, (val != 0), IDLE_CHK_ERROR, "TCM: Interrupt status is not 0"… in lm_idle_chk()
670 …IDLE_CHK_1(0x1F, UCM_REG_UCM_INT_STS, (val != 0), IDLE_CHK_ERROR, "UCM: Interrupt status is not 0"… in lm_idle_chk()
672 …IDLE_CHK_1(0x1F, XCM_REG_XCM_INT_STS, (val != 0), IDLE_CHK_ERROR, "XCM: Interrupt status is not 0"… in lm_idle_chk()
674 …IDLE_CHK_1(0xF, PBF_REG_PBF_INT_STS, (val != 0), IDLE_CHK_ERROR, "PBF: Interrupt status is not 0"); in lm_idle_chk()
676 …IDLE_CHK_1(0x1F, TM_REG_TM_INT_STS, (val != 0), IDLE_CHK_ERROR, "TIMERS: Interrupt status is not 0… in lm_idle_chk()
678 …IDLE_CHK_1(0x1F, DORQ_REG_DORQ_INT_STS, (val != 0), IDLE_CHK_ERROR, "DORQ: Interrupt status is not… in lm_idle_chk()
680 …IDLE_CHK_1(0x1F, SRC_REG_SRC_INT_STS, (val != 0), IDLE_CHK_ERROR, "SRCH: Interrupt status is not 0… in lm_idle_chk()
[all …]
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| /titanic_53/usr/src/uts/sun4u/sys/ |
| H A D | machasi.h | 57 #define ASI_INTR_DISPATCH_STATUS 0x48 /* interrupt vector dispatch status */
58 #define ASI_INTR_RECEIVE_STATUS 0x49 /* interrupt vector receive status */
65 #define ASI_SDB_INTR_W 0x77 /* interrupt vector dispatch */
66 #define ASI_SDB_INTR_R 0x7F /* incoming interrupt vector */
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| /titanic_53/usr/src/uts/intel/ia32/sys/ |
| H A D | psw.h | 53 fl_if : 1, /* interrupt enable */
73 #define PS_IE 0x0200 /* interrupt enable bit */
81 #define PS_VINT 0x80000 /* virtual interrupt flag */
82 #define PS_VINTP 0x100000 /* virtual interrupt pending */
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| /titanic_53/usr/src/uts/sun4u/starcat/sys/ |
| H A D | iosramreg.h | 96 /* interrupt generation */
98 /* interrupt generation */
100 iosram_sbbcr_t int_status; /* 0x2320 - 232f - interrupt status */
101 iosram_sbbcr_t int_enable; /* 0x2330 - 233f - interrupt enables */
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| /titanic_53/usr/src/uts/common/sys/ |
| H A D | rtc.h | 62 #define RTC_RATE6 0x06 /* interrupt rate of 976.562 */
69 #define RTC_PIE 0x40 /* Periodic interrupt enable */
70 #define RTC_AIE 0x20 /* Alarm interrupt enable */
71 #define RTC_UIE 0x10 /* Update ended interrupt enable */
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| /titanic_53/usr/src/man/man7d/ |
| H A D | profile.7d | 8 profile \- DTrace profile interrupt provider
13 time-based interrupt event sources that can be used as DTrace probes.
16 Each profile event source is a time-based interrupt firing every fixed,
|