| /freebsd/sys/contrib/device-tree/src/arm/marvell/ |
| H A D | armada-xp-mv78460.dtsi | 122 interrupt-names = "intx";
124 #interrupt-cells = <1>;
128 interrupt-map-mask = <0 0 0 7>;
129 interrupt-map = <0 0 0 1 &pcie1_intc 0>,
138 pcie1_intc: interrupt-controller {
139 interrupt-controller;
140 #interrupt-cells = <1>;
150 interrupt-names = "intx";
152 #interrupt-cells = <1>;
156 interrupt-map-mask = <0 0 0 7>;
[all …]
|
| H A D | armada-xp-mv78260.dtsi | 101 interrupt-names = "intx";
103 #interrupt-cells = <1>;
107 interrupt-map-mask = <0 0 0 7>;
108 interrupt-map = <0 0 0 1 &pcie1_intc 0>,
117 pcie1_intc: interrupt-controller {
118 interrupt-controller;
119 #interrupt-cells = <1>;
129 interrupt-names = "intx";
131 #interrupt-cells = <1>;
135 interrupt-map-mask = <0 0 0 7>;
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | img,meta-intc.txt | 8 - compatible: Specifies the compatibility list for the interrupt controller.
11 - num-banks: Specifies the number of interrupt banks (each of which can
12 handle 32 interrupt sources).
14 - interrupt-controller: The presence of this property identifies the node
15 as an interrupt controller. No property value shall be defined.
17 - #interrupt-cells: Specifies the number of cells needed to encode an
18 interrupt source. The type shall be a <u32> and the value shall be 2.
22 'interrupt-map' nodes do not have to specify a parent unit address.
28 * Interrupt Specifier Definition
30 Interrupt specifiers consists of 2 cells encoded as follows:
[all …]
|
| H A D | fsl,ls-extirq.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,ls-extirq.yaml#
7 title: Freescale Layerscape External Interrupt Controller
14 LX216xA) support inverting the polarity of certain external interrupt
34 '#interrupt-cells':
40 interrupt-controller: true
45 Specifies the Interrupt Polarity Control Register (INTPCR) in the
46 SCFG or the External Interrupt Control Register (IRQCR) in the ISC.
48 interrupt-map:
51 interrupt-map-mask: true
55 - '#interrupt-cells'
[all …]
|
| H A D | snps,dw-apb-ictl.txt | 1 Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
3 Synopsys DesignWare provides interrupt controller IP for APB known as
4 dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with
5 APB bus, e.g. Marvell Armada 1500. It can also be used as primary interrupt
12 - interrupt-controller: identifies the node as an interrupt controller
13 - #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1
15 Additional required property when it's used as secondary interrupt controller:
16 - interrupts: interrupt reference to primary interrupt controller
18 The interrupt sources map to the corresponding bits in the interrupt
27 /* dw_apb_ictl is used as secondary interrupt controller */
[all …]
|
| H A D | ti,pruss-intc.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/ti,pruss-intc.yaml#
7 title: TI PRU-ICSS Local Interrupt Controller
13 Each PRU-ICSS has a single interrupt controller instance that is common
14 to all the PRU cores. Most interrupt controllers can route 64 input events
19 remaining 8 (2 through 9) connected to external interrupt controllers
25 (host_intr0 through host_intr7) are connected exclusively to the Arm interrupt
32 This interrupt-controller node should be defined as a child node of the
33 corresponding PRUSS node. The node should be named "interrupt-controller".
37 pattern: "^interrupt-controller@[0-9a-f]+$"
59 A shared interrupt ca
[all...] |
| H A D | img,pdc-intc.txt | 1 * ImgTec Powerdown Controller (PDC) Interrupt Controller Binding
4 representation of a PDC IRQ controller. This has a number of input interrupt
5 lines which can wake the system, and are passed on through output interrupt
10 - compatible: Specifies the compatibility list for the interrupt controller.
16 - interrupt-controller: The presence of this property identifies the node
17 as an interrupt controller. No property value shall be defined.
19 - #interrupt-cells: Specifies the number of cells needed to encode an
20 interrupt source. The type shall be a <u32> and the value shall be 2.
26 - interrupts: List of interrupt specifiers. The first specifier shall be the
27 shared SysWake interrupt, and remaining specifies shall be PDC peripheral
[all …]
|
| H A D | brcm,bcm2835-armctrl-ic.txt | 1 BCM2835 Top-Level ("ARMCTRL") Interrupt Controller
3 The BCM2835 contains a custom top-level interrupt controller, which supports
4 72 interrupt sources using a 2-level register scheme. The interrupt
8 The BCM2836 contains the same interrupt controller with the same
9 interrupts, but the per-CPU interrupt controller is the root, and an
10 interrupt there indicates that the ARMCTRL has an interrupt to handle.
17 - interrupt-controller : Identifies the node as an interrupt controlle
[all...] |
| H A D | mti,gic.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
7 title: MIPS Global Interrupt Controller
23 "#interrupt-cells":
26 The 1st cell is the type of interrupt: local or shared defined in the
27 file 'dt-bindings/interrupt-controller/mips-gic.h'. The 2nd cell is the
28 GIC interrupt number. The 3d cell encodes the interrupt flags setting up
30 'dt-bindings/interrupt-controller/irq.h'.
38 interrupt-controller: true
42 Specifies the list of CPU interrupt vectors to which the GIC may not
56 It accepts two values: the 1st is the starting interrupt and the 2nd is
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/pci/ |
| H A D | xlnx,xdma-host.yaml | 38 - description: interrupt asserted when miscellaneous interrupt is received.
39 - description: msi0 interrupt asserted when an MSI is received.
40 - description: msi1 interrupt asserted when an MSI is received.
42 interrupt-names:
48 interrupt-map-mask:
55 interrupt-map:
58 "#interrupt-cells":
61 interrupt-controller:
62 description: identifies the node as an interrupt controller
65 interrupt-controller: true
[all …]
|
| H A D | xlnx,nwl-pcie.yaml | 14 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
34 - description: interrupt asserted when miscellaneous interrupt is received
35 - description: unused interrupt(dummy)
36 - description: interrupt asserted when a legacy interrupt is received
37 - description: msi1 interrupt asserted when an MSI is received
38 - description: msi0 interrupt asserted when an MSI is received
40 interrupt-names:
48 interrupt-map-mask:
55 "#interrupt-cells":
61 interrupt-map:
[all …]
|
| H A D | xilinx-pcie.txt | 6 - #interrupt-cells: specifies the number of cells needed to encode an
7 interrupt source. The value must be 1.
11 - interrupts: Should contain AXI PCIe interrupt
12 - interrupt-map-mask,
13 interrupt-map: standard PCI properties to define the mapping of the
14 PCI interface to interrupt numbers.
23 Interrupt controller child node
26 - interrupt-controller: identifies the node as an interrupt controller
29 - #interrupt-cells: specifies the number of cells needed to encode an
30 interrupt source. The value must be 1.
[all …]
|
| H A D | ralink,rt3883-pci.txt | 29 interrupt controller and the PCI host bridge.
31 a) Interrupt controller:
35 - interrupt-controller: identifies the node as an interrupt controller
38 address. The value must be 0. As such, 'interrupt-map' nodes do not
41 - #interrupt-cells: specifies the number of cells needed to encode an
42 interrupt source. The value must be 1.
44 - interrupts: specifies the interrupt source of the parent interrupt
45 controller. The format of the interrupt specifier depends on the
46 parent interrupt controller.
58 - #interrupt-cells: specifies the number of cells needed to encode an
[all …]
|
| H A D | mediatek-pcie.txt | 42 - #interrupt-cells: Size representation for interrupts (must be 1)
43 - interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
52 -interrupts: A list of interrupt outputs of the controller, must have one
54 - interrupt-names: Must include the following entries:
55 - "pcie_irq": The interrupt that is asserted when an MSI/INTX is received
67 - #interrupt-cells: Must be 1
68 - interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
95 #interrupt-cells = <1>;
96 interrupt-map-mask = <0xf800 0 0 0>;
97 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
[all …]
|
| H A D | xilinx-nwl-pcie.txt | 7 - #interrupt-cells: specifies the number of cells needed to encode an
8 interrupt source. The value must be 1.
16 - interrupts: Should contain NWL PCIe interrupt
17 - interrupt-names: Must include the following entries:
18 "msi1, msi0": interrupt asserted when an MSI is received
19 "intx": interrupt asserted when a legacy interrupt is received
20 "misc": interrupt asserted when miscellaneous interrupt is received
21 - interrupt-map-mask and interrupt-map: standard PCI properties to define the
22 mapping of the PCI interface to interrupt numbers.
29 - legacy-interrupt-controller: Interrupt controller device node for Legacy
[all …]
|
| /freebsd/sys/contrib/device-tree/src/mips/brcm/ |
| H A D | bcm7125.dtsi | 30 cpu_intc: interrupt-controller {
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
35 #interrupt-cells = <1>;
59 periph_intc: interrupt-controller@441400 {
63 interrupt-controller;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
70 sun_l2_intc: interrupt-controller@401800 {
73 interrupt-controller;
[all …]
|
| H A D | bcm7420.dtsi | 30 cpu_intc: interrupt-controller {
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
35 #interrupt-cells = <1>;
59 periph_intc: interrupt-controller@441400 {
63 interrupt-controller;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
70 sun_l2_intc: interrupt-controller@401800 {
73 interrupt-controller;
[all …]
|
| /freebsd/sys/contrib/device-tree/src/mips/loongson/ |
| H A D | loongson64-2k1000.dtsi | 5 #include <dt-bindings/interrupt-controller/irq.h>
32 cpuintc: interrupt-controller {
34 #interrupt-cells = <1>;
35 interrupt-controller;
36 compatible = "mti,cpu-interrupt-controller";
59 liointc0: interrupt-controller@1fe11400 {
66 interrupt-controller;
67 #interrupt-cells = <2>;
69 interrupt-parent = <&cpuintc>;
71 interrupt-names = "int0";
[all …]
|
| /freebsd/sys/dts/arm/ |
| H A D | imx53x.dtsi | 70 tzic: tz-interrupt-controller@0fffc000 {
72 interrupt-controller;
73 #interrupt-cells = <1>;
95 interrupt-parent = <&tzic>;
102 interrupt-parent = <&tzic>;
116 interrupt-parent = <&tzic>;
129 interrupt-parent = <&tzic>;
134 interrupt-controller;
135 #interrupt-cells = <1>;
142 interrupt-parent = <&tzic>;
[all …]
|
| /freebsd/sys/contrib/device-tree/src/loongarch/ |
| H A D | loongson-2k0500.dtsi | 8 #include <dt-bindings/interrupt-controller/irq.h>
34 cpuintc: interrupt-controller {
35 compatible = "loongson,cpu-interrupt-controller";
36 #interrupt-cells = <1>;
37 interrupt-controller;
90 interrupt-parent = <&eiointc>;
100 interrupt-parent = <&eiointc>;
110 interrupt-parent = <&eiointc>;
120 interrupt-parent = <&eiointc>;
127 liointc0: interrupt-controller@1fe11400 {
[all …]
|
| H A D | loongson-2k1000.dtsi | 8 #include <dt-bindings/interrupt-controller/irq.h>
42 cpuintc: interrupt-controller {
43 compatible = "loongson,cpu-interrupt-controller";
44 #interrupt-cells = <1>;
45 interrupt-controller;
110 liointc0: interrupt-controller@1fe01400 {
116 interrupt-controller;
117 #interrupt-cells = <2>;
118 interrupt-parent = <&cpuintc>;
120 interrupt-names = "int0";
[all …]
|
| /freebsd/sys/contrib/device-tree/src/arm64/exynos/ |
| H A D | exynos7-pinctrl.dtsi | 19 interrupt-controller;
20 interrupt-parent = <&gic>;
21 #interrupt-cells = <2>;
36 interrupt-controller;
37 interrupt-parent = <&gic>;
38 #interrupt-cells = <2>;
53 interrupt-controller;
54 #interrupt-cells = <2>;
61 interrupt-controller;
62 #interrupt-cells = <2>;
[all …]
|
| H A D | exynos5433-pinctrl.dtsi | 36 interrupt-controller;
37 interrupt-parent = <&gic>;
46 #interrupt-cells = <2>;
53 interrupt-controller;
54 interrupt-parent = <&gic>;
63 #interrupt-cells = <2>;
70 interrupt-controller;
71 #interrupt-cells = <2>;
78 interrupt-controller;
79 #interrupt-cells = <2>;
[all …]
|
| /freebsd/contrib/bmake/unit-tests/ |
| H A D | cmd-interrupt.mk | 1 # $NetBSD: cmd-interrupt.mk,v 1.5 2024/07/13 15:10:06 rillig Exp $
21 all: interrupt-ordinary
22 all: interrupt-phony
23 all: interrupt-precious
24 all: interrupt-compat
28 @rm -f cmd-interrupt-ordinary cmd-interrupt-phony
29 @rm -f cmd-interrupt-precious cmd-interrupt-compat
31 interrupt-ordinary:
32 @${.MAKE} ${MAKEFLAGS} -f ${MAKEFILE} cmd-interrupt-ordinary || true
34 @echo ${.TARGET}: ${exists(././cmd-interrupt-ordinary) :? error : ok }
[all …]
|
| /freebsd/share/man/man9/ |
| H A D | swi.9 | 31 .Nd register and schedule software interrupt handlers
52 These functions are used to register and schedule software interrupt handlers.
53 Software interrupt handlers are attached to a software interrupt thread, just
54 as hardware interrupt handlers are attached to a hardware interrupt thread.
56 Software interrupt handlers can be used to queue up less critical processing
57 inside of hardware interrupt handlers so that the work can be done at a later
59 Software interrupt threads are different from other kernel threads in that they
60 are treated as an interrupt thread.
61 This means that time spent executing these threads is counted as interrupt
66 function is used to add a new software interrupt handler to a specified
[all …]
|