| /titanic_51/usr/src/man/man9f/ |
| H A D | ddi_umem_alloc.9f | 157 For driver interrupt routines.
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| H A D | kstat_create.9f | 97 Interrupt; only one data record per \fBkstat\fR.
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| H A D | mkiocb.9f | 152 The \fBmkiocb()\fR function can be called from user, interrupt, or kernel
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| H A D | allocb.9f | 144 The \fBallocb()\fR function can be called from user, interrupt, or kernel
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| H A D | csx_ModifyConfiguration.9f | 89 previously selected system interrupt.
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| /titanic_51/usr/src/uts/common/xen/public/hvm/ |
| H A D | params.h | 32 * val[63:56] == 0: val[55:0] is a delivery GSI (Global System Interrupt).
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| /titanic_51/usr/src/uts/i86pc/sys/ |
| H A D | psm_common.h | 72 * referencing an interrupt link device the configured irq for the device.
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| /titanic_51/usr/src/common/nvpair/ |
| H A D | nvpair_alloc_fixed.c | 46 * This allocator is designed for the usage in interrupt context when
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| /titanic_51/usr/src/boot/sys/boot/arm/at91/libat91/ |
| H A D | arm_init.S | 55 B swivec @; Software Interrupt
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| /titanic_51/usr/src/uts/sun4v/os/ |
| H A D | cpc_subr.c | 48 uint64_t cpc_level15_inum = 0; /* used in interrupt.s */
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| /titanic_51/usr/src/uts/sun4u/sys/pci/ |
| H A D | pci_cb.h | 67 pci_ign_t cb_ign; /* 1st-attached-side interrupt grp# */
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| H A D | pcipsy.h | 58 * Offsets of registers in the interrupt block:
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| /titanic_51/usr/src/uts/sun4u/sys/i2c/nexus/ |
| H A D | pcf8584.h | 172 * generic interrupt return values
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| /titanic_51/usr/src/uts/sun4u/serengeti/sys/ |
| H A D | sgsbbc_iosram_priv.h | 128 * interrupt handlers
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| /titanic_51/usr/src/lib/libc/port/stdio/ |
| H A D | getpass.c | 89 (void) sigaction(SIGINT, &act, &osigint); /* trap interrupt */ in __getpass()
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| /titanic_51/usr/src/uts/common/os/ |
| H A D | cpu_intr.c | 113 * of I/O interrupt participation. This also permits the
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| H A D | cpu.c | 524 * (kernel preemption disabled; high pil; strongly bound; interrupt thread)
539 * A highlevel interrupt must not modify t_nomigrate or in thread_nomigrate()
541 * interrupt thread cannot migrate and we can avoid the in thread_nomigrate()
638 * store to t_weakbound_cpu and the interrupt calls in thread_nomigrate()
986 * paused match those for code executed at high-level interrupt
1310 * Take the CPU out of interrupt participation so we won't find in cpu_offline()
1313 * run anything but interrupt thread... this is indicated by in cpu_offline()
1344 * Inactive interrupt threads are OK (they'll be in TS_FREE in cpu_offline()
1349 * that permits interrupt threads to be active (or bypassed). in cpu_offline()
2890 * should include both the interrupt thread in cpu_destroy_bound_threads()
[all...] |
| /titanic_51/usr/src/cmd/mail/ |
| H A D | mkdead.c | 107 dflag = 2; /* do not send back letter on interrupt */ in savdead()
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| /titanic_51/usr/src/uts/common/disp/ |
| H A D | disp.c | 94 pri_t intr_pri; /* interrupt thread priority base level */
106 * If this is set, only interrupt threads will cause kernel preemptions.
108 * will either be the max sysclass pri or the min interrupt pri.
189 * compute new interrupt thread base priority in disp_setup()
761 * interrupt threads, which will be the only threads on the CPU's own in disp()
878 * We are an interrupt thread. Setup and return in swtch()
1985 * halted, or busy servicing an interrupt), in disp_getwork()
2439 * If an interrupt thread is busy, but the in disp_bound_common()
2494 * to the given processor, including interrupt threads.
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| /titanic_51/usr/src/uts/i86xpv/os/ |
| H A D | xpv_panic.c | 79 static gate_desc_t xpv_panic_idt[NIDT]; /* interrupt descriptor table */
548 /* The one interrupt we expect to get is from the APIC timer. */ in switch_to_xpv_panic_idt()
585 * one timeout interval. Program the timer to send us an interrupt in xpv_apic_clkinit()
613 xpv_panic_printf("Unexpected interrupt received.\n"); in xpv_interrupt()
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| /titanic_51/usr/src/uts/sun4u/sys/ |
| H A D | envctrl_ue450.h | 224 * | L | X | 1 | H | R/W Interrupt Vector (S3)
226 * | X | 0 | X | L | R Interrupt Vector (S3) ack cycle
349 * you must look at the CSR to see which ports caused the interrupt
659 ddi_iblock_cookie_t ic_trap_cookie; /* interrupt cookie */
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| /titanic_51/usr/src/uts/common/sys/nxge/ |
| H A D | nxge_impl.h | 608 * - interrupt handler function.
610 * Generic system interrupt handler with two arguments:
615 * Logical device interrupt handler with two arguments:
1174 // NIU-specific interrupt API
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| /titanic_51/usr/src/uts/intel/io/dktp/controller/ata/ |
| H A D | ata_disk.c | 1956 * clear the interrupt disable bit after being resumed. The in ata_disk_start_common()
2020 * reset the PCIIDE Controller's interrupt and error status bits in ata_disk_start_dma_in()
2061 * reset the PCIIDE Controller's interrupt and error status bits in ata_disk_start_dma_out()
2147 * of data. Have to busy wait because there's no interrupt for in ata_disk_start_pio_out()
2165 * Tell the upper layer to fake a hardware interrupt which in ata_disk_start_pio_out()
2238 * Interrupt callbacks
2367 * wait for the next interrupt. in ata_disk_intr_pio_in()
2427 * check for final interrupt on write command in ata_disk_intr_pio_out()
2476 * Wait for the next interrupt before checking the transfer in ata_disk_intr_pio_out()
2631 * interrupt in ata_disk_pio_xfer_data_out()
[all...] |
| /titanic_51/usr/src/uts/common/io/nxge/ |
| H A D | nxge_txdma.c | 427 /* Add interrupt handler for this channel. */ in nxge_enable_txdma_channel()
1103 * Process a TDC interrupt
1163 * This interrupt handler is for a specific in nxge_tx_intr()
1261 * and reset after injecting an interrupt error. in nxge_txdma_channel_disable()
1306 * TDMC_INTR_DBG DMC + 0x40060 Transmit DMA Interrupt Debug
1417 * TDMC_INTR_DBG DMC + 0x40060 Transmit DMA Interrupt Debug
1908 * TDMC_INTR_DBG DMC + 0x40060 Transmit DMA Interrupt Debug
2719 * interrupt thread can all call the transmit reclaim, in nxge_unmap_txdma_channel_buf_ring()
2977 /* Set up the interrupt event masks. */ in nxge_txdma_stop_channel()
3616 * TDMC_INTR_DBG DMC + 0x40060 Transmit DMA Interrupt Debu
[all...] |
| /titanic_51/usr/src/uts/common/io/hxge/ |
| H A D | hxge_rxdma.c | 1030 * the race condition with the interrupt thread that in hxge_freeb()
1114 * This interrupt handler is for a specific receive dma channel. in hxge_rx_intr()
1161 * Enable the mailbox update interrupt if we want to use in hxge_rx_intr()
1186 * Disarm the group, if we are not a shared interrupt. in hxge_rx_intr()
1211 * Enable polling for a ring. Interrupt for the ring is disabled when
1212 * the hxge interrupt comes (see hxge_rx_intr).
1257 * Disable polling for a ring and enable its interrupt.
1277 * Disable polling: enable interrupt in hxge_disable_poll()
3375 /* Set up the interrupt event masks. */ in hxge_rxdma_start_channel()
3463 /* Set up the interrupt even in hxge_rxdma_stop_channel()
[all...] |