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/titanic_53/usr/src/uts/common/io/ib/adapters/tavor/
H A Dtavor_qp.c1277 * Context: Can be called from interrupt or base context.
1372 * Since we may be in the interrupt context (or subsequently raised in tavor_qp_query()
1373 * to interrupt level by priority inversion), we do not want to block in tavor_qp_query()
1534 * Context: Can be called from interrupt or base context.
1765 * Context: Can be called from interrupt or base context.
1796 * Context: Can be called from interrupt or base context.
1907 * Context: Can be called from interrupt or base context.
1975 * Context: Can be called from interrupt or base context.
/titanic_53/usr/src/man/man9f/
H A Dddi_fm_ereport_post.9f174 high-level interrupt context.
H A Dscsi_errmsg.9f188 The \fBscsi_errmsg()\fR function may be called from user, interrupt, or kernel
H A Dtestb.9f59 The \fBtestb()\fR function can be called user, interrupt, or kernel context.
H A Ddrv_getparm.9f152 be called from user, interrupt, or kernel context when using the \fBLBOLT\fR or
H A Dddi_fm_acc_err_get.9f116 called from user, kernel, or high-level interrupt context.
H A Dnet_inject.9f132 The \fBnet_inject()\fR function may be called from user, kernel, or interrupt
H A Dddi_umem_lock.9f183 \fBddi_umem_unlock()\fR from user, kernel, and interrupt contexts.
H A Dusb_client_attach.9f150 Called from interrupt context. Not called from an attach routine context.
H A Dscsi_alloc_consistent_buf.9f147 from user-level code. Otherwise, it may be called fromuser, interrupt, or
/titanic_53/usr/src/uts/common/sys/
H A Dttcompat.h48 char t_intrc; /* interrupt */
/titanic_53/usr/src/uts/sun4u/opl/sys/pcicmu/
H A Dpcmu_err.h49 * Since pcmu_pbm_err_handler() is called by various interrupt/trap/callback
/titanic_53/usr/src/uts/sparc/v7/sys/
H A Dpsr.h52 #define PSR_PIL 0x00000F00 /* processor interrupt level */
/titanic_53/usr/src/head/
H A Ddial.h54 #define INTRPT (-1) /* interrupt occured */
/titanic_53/usr/src/man/man1m/
H A Dpsrinfo.1m25 with its own interrupt \fBID\fR, capable of executing independent threads.
/titanic_53/usr/src/cmd/rexd/
H A Drex.h93 struct tchars more; /* interrupt, kill characters, etc. */
/titanic_53/usr/src/uts/sun/sys/dada/adapters/
H A Datapi.h28 * Status bits from ATAPI Interrupt reason register (AT_COUNT) register
/titanic_53/usr/src/grub/grub-0.97/netboot/
H A Dpic8259.h2 * Basic support for controlling the 8259 Programmable Interrupt Controllers.
H A Deepro100.c167 #define DRVR_INT 0x0200 /* Driver generated interrupt. */
185 CmdIntr = 0x2000, /* Interrupt after completion. */
398 /* Acknowledge all of the current interrupt sources ASAP. */ in eepro100_transmit()
553 /* Mask off our interrupt line -- it is unmasked after reset */ in eepro100_disable()
/titanic_53/usr/src/uts/sun4u/serengeti/sys/
H A Dsgsbbc_iosram.h84 * interrupt related routines
/titanic_53/usr/src/uts/sun4u/os/
H A Dcpc_subr.c49 uint64_t cpc_level15_inum = 0; /* used in interrupt.s */
/titanic_53/usr/src/uts/sun4u/opl/sys/
H A Doplkm.h46 ddi_iblock_cookie_t km_ibcookie; /* Interrupt block cookie */
/titanic_53/usr/src/uts/i86pc/io/pci/
H A Dpci_tools.c98 /* Create pcitool nodes for register access and interrupt routing. */ in pcitool_init()
203 * CPU value, not an ihdl_plat_t as used for global interrupt handling. in pcitool_set_intr()
338 * global interrupt handling. in pcitool_get_intr()
505 * Main function for handling interrupt CPU binding requests and queries.
/titanic_53/usr/src/uts/intel/io/amd8111s/
H A Damd8111s_hw.h288 /* DELAY INTERRUPT REGISTER */
296 /* INTERRUPT REGISTER */
920 /* For interrupt delay */
1044 /* Interrupt Handling */
/titanic_53/usr/src/uts/common/io/nge/
H A Dnge_chip.h103 * Master interrupt
130 * Master interrupt Mask
989 * Mii interrupt register
1006 * Mii interrupt mask

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