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Searched +full:inline +full:- +full:crypto +full:- +full:engine (Results 1 – 25 of 69) sorted by relevance

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/linux/drivers/soc/qcom/
H A Dice.c1 // SPDX-License-Identifier: GPL-2.0
3 * Qualcomm ICE (Inline Crypto Engine) support.
5 * Copyright (c) 2013-2019, The Linux Foundation. All rights reserved.
82 #define qcom_ice_writel(engine, val, reg) \ argument
83 writel((val), (engine)->base + (reg))
85 #define qcom_ice_readl(engine, reg) \ argument
86 readl((engine)->base + (reg))
105 struct device *dev = ice->dev; in qcom_ice_check_supported()
117 dev_info(dev, "Found QC Inline Crypto Engine (ICE) v%d.%d.%d\n", in qcom_ice_check_supported()
140 * ICE-capable storage driver(s) need to know early on whether to in qcom_ice_check_supported()
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/linux/drivers/crypto/caam/
H A Dintern.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright 2008-2011 Freescale Semiconductor, Inc.
14 #include <crypto/engine.h>
16 /* Currently comes from Kconfig param as a ^2 (driver-required) */
20 * Maximum size for crypto-engine software queue based on Job Ring
21 * size (JOBR_DEPTH) and a THRESHOLD (reserved for the non-crypto-API
22 * requests that are not passed through crypto-engine)
25 #define CRYPTO_ENGINE_MAX_QLEN (JOBR_DEPTH - THRESHOLD)
39 * Storage for tracking each in-process entry moving across a ring
60 /* Private sub-storage for a single JobR */
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H A Dcaamhash.c1 // SPDX-License-Identifier: GPL-2.0+
3 * caam - Freescale FSL CAAM support for ahash functions of crypto API
6 * Copyright 2018-2019, 2023 NXP
8 * Based on caamalg.c crypto API driver.
13 * --------------- ---------------
14 * | JobDesc #1 |-------------------->| ShareDesc |
16 * --------------- | (operation) |
17 * ---------------
21 * --------------- ---------------
22 * | JobDesc #2 |-------------------->| ShareDesc |
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/linux/drivers/crypto/ccp/
H A Dccp-crypto.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * AMD Cryptographic Coprocessor (CCP) crypto API support
16 #include <crypto/algapi.h>
17 #include <crypto/aes.h>
18 #include <crypto/internal/aead.h>
19 #include <crypto/aead.h>
20 #include <crypto/ctr.h>
21 #include <crypto/hash.h>
22 #include <crypto/sha1.h>
23 #include <crypto/sha2.h>
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H A Dccp-crypto-rsa.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * AMD Cryptographic Coprocessor (CCP) RSA crypto API support
13 #include <linux/crypto.h>
14 #include <crypto/algapi.h>
15 #include <crypto/internal/rsa.h>
16 #include <crypto/internal/akcipher.h>
17 #include <crypto/akcipher.h>
18 #include <crypto/scatterwalk.h>
20 #include "ccp-crypto.h"
22 static inline struct akcipher_request *akcipher_request_cast( in akcipher_request_cast()
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/linux/drivers/crypto/virtio/
H A Dvirtio_crypto_common.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* Common header for Virtio crypto device.
11 #include <linux/crypto.h>
14 #include <crypto/aead.h>
15 #include <crypto/aes.h>
16 #include <crypto/engine.h>
31 struct crypto_engine *engine; member
130 struct crypto_engine *engine, void *vreq);
135 static inline int virtio_crypto_get_current_node(void) in virtio_crypto_get_current_node()
/linux/include/crypto/
H A Dpcrypt.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * pcrypt - Parallel crypto engine.
13 #include <linux/crypto.h>
22 static inline void *pcrypt_request_ctx(struct pcrypt_request *req) in pcrypt_request_ctx()
24 return req->__ctx; in pcrypt_request_ctx()
27 static inline
30 return &req->padata; in pcrypt_request_padata()
33 static inline
/linux/drivers/mmc/host/
H A Dcqhci-crypto.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * CQHCI crypto engine (inline encryption) support
20 * Returns the crypto bits that should be set in bits 64-127 of the
23 static inline u64 cqhci_crypto_prep_task_desc(struct mmc_request *mrq) in cqhci_crypto_prep_task_desc()
25 if (!mrq->crypto_ctx) in cqhci_crypto_prep_task_desc()
28 /* We set max_dun_bytes_supported=4, so all DUNs should be 32-bit. */ in cqhci_crypto_prep_task_desc()
29 WARN_ON_ONCE(mrq->crypto_ctx->bc_dun[0] > U32_MAX); in cqhci_crypto_prep_task_desc()
32 CQHCI_CRYPTO_KEYSLOT(mrq->crypto_key_slot) | in cqhci_crypto_prep_task_desc()
33 mrq->crypto_ctx->bc_dun[0]; in cqhci_crypto_prep_task_desc()
38 static inline int cqhci_crypto_init(struct cqhci_host *host) in cqhci_crypto_init()
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H A Dcqhci-crypto.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * CQHCI crypto engine (inline encryption) support
8 #include <linux/blk-crypto.h>
9 #include <linux/blk-crypto-profile.h>
12 #include "cqhci-crypto.h"
14 /* Map from blk-crypto modes to CQHCI crypto algorithm IDs and key sizes */
25 static inline struct cqhci_host *
28 return mmc_from_crypto_profile(profile)->cqe_private; in cqhci_host_from_crypto_profile()
35 u32 slot_offset = cq_host->crypto_cfg_register + slot * sizeof(*cfg); in cqhci_crypto_program_key()
39 cqhci_writel(cq_host, 0, slot_offset + 16 * sizeof(cfg->reg_val[0])); in cqhci_crypto_program_key()
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/linux/Documentation/devicetree/bindings/mmc/
H A Dsdhci-msm.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/sdhci-msm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SDHCI controller (sdhci-msm)
10 - Bjorn Andersson <andersson@kernel.org>
11 - Konrad Dybcio <konradybcio@kernel.org>
20 - enum:
21 - qcom,sdhci-msm-v4
23 - items:
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/linux/drivers/crypto/ccree/
H A Dcc_driver.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */
5 * ARM CryptoCell Linux Crypto Driver
16 #include <linux/dma-mapping.h>
17 #include <crypto/algapi.h>
18 #include <crypto/internal/skcipher.h>
19 #include <crypto/aes.h>
20 #include <crypto/sha1.h>
21 #include <crypto/sha2.h>
22 #include <crypto/aead.h>
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/linux/drivers/crypto/intel/keembay/
H A Docs-aes.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Intel Keem Bay OCS AES Crypto Driver.
5 * Copyright (C) 2018-2020 Intel Corporation
11 #include <linux/dma-mapping.h>
35 * struct ocs_aes_dev - AES device context.
43 * @engine: Crypto engine for the device.
52 struct crypto_engine *engine; member
56 * struct ocs_dll_desc - Descriptor of an OCS DMA Linked List.
81 * ocs_aes_bypass_op() - Use OCS DMA to copy data.
88 static inline int ocs_aes_bypass_op(struct ocs_aes_dev *aes_dev, in ocs_aes_bypass_op()
H A Docs-aes.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Intel Keem Bay OCS AES Crypto Driver.
5 * Copyright (C) 2018-2020 Intel Corporation
8 #include <linux/dma-mapping.h>
17 #include <crypto/aes.h>
18 #include <crypto/gcm.h>
20 #include "ocs-aes.h"
131 * 11-bit value, but it is actually 10-bits.
137 * before the tag is written. For 128-bit mode this required delay is 28 OCS
138 * clock cycles. For 256-bit mode it is 36 OCS clock cycles.
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H A Dkeembay-ocs-hcu-core.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Intel Keem Bay OCS HCU Crypto Driver.
5 * Copyright (C) 2018-2020 Intel Corporation
8 #include <crypto/engine.h>
9 #include <crypto/hmac.h>
10 #include <crypto/internal/hash.h>
11 #include <crypto/scatterwalk.h>
12 #include <crypto/sha2.h>
13 #include <crypto/sm3.h>
15 #include <linux/dma-mapping.h>
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/linux/drivers/mmc/core/
H A Dcrypto.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * MMC crypto engine (inline encryption) support
8 #include <linux/blk-crypto.h>
12 #include "crypto.h"
18 if (host->caps2 & MMC_CAP2_CRYPTO) in mmc_crypto_set_initial_state()
19 blk_crypto_reprogram_all_keys(&host->crypto_profile); in mmc_crypto_set_initial_state()
24 if (host->caps2 & MMC_CAP2_CRYPTO) in mmc_crypto_setup_queue()
25 blk_crypto_register(&host->crypto_profile, q); in mmc_crypto_setup_queue()
32 struct mmc_request *mrq = &mqrq->brq.mrq; in mmc_crypto_prepare_req()
35 if (!req->crypt_ctx) in mmc_crypto_prepare_req()
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H A Dcrypto.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * MMC crypto engine (inline encryption) support
25 static inline void mmc_crypto_set_initial_state(struct mmc_host *host) in mmc_crypto_set_initial_state()
29 static inline void mmc_crypto_setup_queue(struct request_queue *q, in mmc_crypto_setup_queue()
34 static inline void mmc_crypto_prepare_req(struct mmc_queue_req *mqrq) in mmc_crypto_prepare_req()
/linux/include/linux/
H A Dccp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
17 #include <crypto/aes.h>
18 #include <crypto/sha1.h>
19 #include <crypto/sha2.h>
27 * ccp_present - check if a CCP device is present
29 * Returns zero if a CCP device is present, -ENODEV otherwise.
34 #define CCP_VMASK ((unsigned int)((1 << CCP_VSIZE) - 1))
39 * ccp_version - get the version of the CCP
46 * ccp_enqueue_cmd - queue an operation for processing by the CCP
55 * result in a return code of -EBUSY.
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/linux/drivers/crypto/starfive/
H A Djh7110-aes.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <crypto/engine.h>
9 #include <crypto/gcm.h>
10 #include <crypto/internal/aead.h>
11 #include <crypto/internal/skcipher.h>
12 #include <crypto/scatterwalk.h>
13 #include "jh7110-cryp.h"
52 static inline int starfive_aes_wait_busy(struct starfive_cryp_dev *cryp) in starfive_aes_wait_busy()
56 return readl_relaxed_poll_timeout(cryp->base + STARFIVE_AES_CSR, status, in starfive_aes_wait_busy()
60 static inline int starfive_aes_wait_keydone(struct starfive_cryp_dev *cryp) in starfive_aes_wait_keydone()
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H A Djh7110-hash.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <crypto/engine.h>
10 #include <crypto/internal/hash.h>
11 #include <crypto/scatterwalk.h>
12 #include "jh7110-cryp.h"
15 #include <linux/dma-direct.h>
39 static inline int starfive_hash_wait_busy(struct starfive_cryp_dev *cryp) in starfive_hash_wait_busy()
43 return readl_relaxed_poll_timeout(cryp->base + STARFIVE_HASH_SHACSR, status, in starfive_hash_wait_busy()
47 static inline int starfive_hash_wait_hmac_done(struct starfive_cryp_dev *cryp) in starfive_hash_wait_hmac_done()
51 return readl_relaxed_poll_timeout(cryp->base + STARFIVE_HASH_SHACSR, status, in starfive_hash_wait_hmac_done()
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/linux/drivers/net/wireless/ath/ath10k/
H A Dcore.h1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
5 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
46 #define ATH10K_DEFAULT_NOISE_FLOOR -95
67 /* SMBIOS type structure length (excluding strings-set) */
93 static inline const char *ath10k_bus_str(enum ath10k_bus bus) in ath10k_bus_str()
138 static inline struct ath10k_skb_cb *ATH10K_SKB_CB(struct sk_buff *skb) in ATH10K_SKB_CB()
142 return (struct ath10k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data; in ATH10K_SKB_CB()
145 static inline struct ath10k_skb_rxcb *ATH10K_SKB_RXCB(struct sk_buff *skb) in ATH10K_SKB_RXCB()
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/linux/drivers/crypto/
H A Dhifn_795x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
16 #include <linux/dma-mapping.h>
19 #include <linux/crypto.h>
23 #include <crypto/algapi.h>
24 #include <crypto/internal/des.h>
25 #include <crypto/internal/skcipher.h>
199 #define HIFN_DMACSR_D_CTRL_NOP 0x00000000 /* Dest. Control: no-op */
208 #define HIFN_DMACSR_R_CTRL_NOP 0x00000000 /* Result Control: no-op */
217 #define HIFN_DMACSR_S_CTRL_NOP 0x00000000 /* Source Control: no-op */
227 #define HIFN_DMACSR_C_CTRL_NOP 0x00000000 /* Command Control: no-op */
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H A Dgeode-aes.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Copyright (C) 2004-2006, Advanced Micro Devices, Inc.
9 #include <linux/crypto.h>
11 #include <crypto/algapi.h>
12 #include <crypto/aes.h>
13 #include <crypto/internal/cipher.h>
14 #include <crypto/internal/skcipher.h>
19 #include "geode-aes.h"
27 static inline void
37 static inline void
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H A Dpadlock-aes.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Support for VIA PadLock hardware crypto engine.
11 #include <crypto/algapi.h>
12 #include <crypto/aes.h>
13 #include <crypto/internal/skcipher.h>
14 #include <crypto/padlock.h>
76 static inline int
87 static inline struct aes_ctx *aes_ctx_common(void *ctx) in aes_ctx_common()
97 static inline struct aes_ctx *aes_ctx(struct crypto_tfm *tfm) in aes_ctx()
102 static inline struct aes_ctx *skcipher_aes_ctx(struct crypto_skcipher *tfm) in skcipher_aes_ctx()
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/linux/arch/mips/include/asm/octeon/
H A Docteon-feature.h7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
34 #include <asm/octeon/cvmx-mio-defs.h>
35 #include <asm/octeon/cvmx-rnm-defs.h>
40 /* CN68XX has different fields in word0 - word2 */
47 /* Does this Octeon support the ZIP offload engine? */
92 OCTEON_HAS_CRYPTO = 0x0001, /* Crypto acceleration using COP2 */
97 * octeon_has_crypto() - Check if this OCTEON has crypto acceleration support.
99 * Returns: Non-zero if the feature exists. Zero if the feature does not exist.
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/linux/drivers/crypto/tegra/
H A Dtegra-se-aes.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
4 * Crypto driver to handle block cipher algorithms using NVIDIA Security Engine.
8 #include <linux/dma-mapping.h>
13 #include <crypto/aead.h>
14 #include <crypto/aes.h>
15 #include <crypto/engine.h>
16 #include <crypto/gcm.h>
17 #include <crypto/scatterwalk.h>
18 #include <crypto/xts.h>
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