Searched +full:imx8qxp +full:- +full:display +full:- +full:pixel +full:- +full:link +full:- +full:msi +full:- +full:bus (Results 1 – 1 of 1) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Freescale i.MX8qxp Pixel Link Medium Speed Interconnect (MSI) Bus10 - Liu Ying <victor.liu@nxp.com>13 i.MX8qxp pixel link MSI bus is used to control settings of PHYs, I/Os14 sitting together with the PHYs. It is not the same as the MSI bus coming18 i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks,19 that is, MSI clock and AHB clock, need to be enabled so that peripherals[all …]