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/linux/Documentation/devicetree/bindings/usb/
H A Dhisilicon,histb-xhci.txt6 - compatible: should be "hisilicon,hi3798cv200-xhci"
7 - reg: specifies physical base address and size of the registers
8 - interrupts : interrupt used by the controller
9 - clocks: a list of phandle + clock-specifier pairs, one for each
10 entry in clock-names
11 - clock-names: must contain
16 - resets: a list of phandle and reset specifier pairs as listed in
17 reset-names property.
18 - reset-names: must contain
20 - phys: a list of phandle + phy specifier pairs
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H A Dusb-xhci.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/usb-xhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mathias Nyman <mathias.nyman@intel.com>
13 - $ref: usb-hcd.yaml#
16 usb2-lpm-disable:
20 usb3-lpm-capable:
24 quirk-broken-port-ped:
28 imod-interval-ns:
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H A Dmediatek,mtk-xhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/mediatek,mtk-xhci.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 - $ref: usb-xhci.yaml
19 case 2: supports dual-role mode, and the host is based on xHCI driver.
25 - enum:
26 - mediatek,mt2701-xhci
27 - mediatek,mt2712-xhci
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/linux/drivers/usb/host/
H A Dxhci.h1 /* SPDX-License-Identifier: GPL-2.0 */
19 #include <linux/io-64-nonatomic-lo-hi.h>
20 #include <linux/io-64-nonatomic-hi-lo.h>
22 /* Code sharing between pci-quirks and xhci hcd */
23 #include "xhci-ext-caps.h"
24 #include "pci-quirks.h"
26 #include "xhci-port.h"
27 #include "xhci-caps.h"
35 /* Max number of USB devices for any host controller - limit in section 6.1 */
37 /* Section 5.3.3 - MaxPorts */
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H A Dxhci.c1 // SPDX-License-Identifier: GPL-2.0
22 #include <linux/dma-mapping.h>
23 #include <linux/usb/xhci-sideband.h>
26 #include "xhci-trace.h"
27 #include "xhci-debugfs.h"
28 #include "xhci-dbgcap.h"
48 if (!td || !td->start_seg) in td_on_ring()
51 xhci_for_each_ring_seg(ring->first_seg, seg) { in td_on_ring()
52 if (seg == td->start_seg) in td_on_ring()
60 * xhci_handshake - spin reading hc until handshake completes or fails
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H A Dxhci-plat.c1 // SPDX-License-Identifier: GPL-2.0
3 * xhci-plat.c - xHCI host controller driver platform Bus Glue.
5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com
12 #include <linux/dma-mapping.h>
25 #include "xhci-plat.h"
26 #include "xhci-mvebu.h"
43 if (priv->plat_start) in xhci_priv_plat_start()
44 priv->plat_start(hcd); in xhci_priv_plat_start()
51 if (!priv->init_quirk) in xhci_priv_init_quirk()
54 return priv->init_quirk(hcd); in xhci_priv_init_quirk()
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H A Dxhci-mtk.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/dma-mapping.h>
25 #include "xhci-mtk.h"
135 * MT8195 has 4 controllers, the controller1~3's default SOF/ITP interval
141 struct device *dev = mtk->dev; in xhci_mtk_set_frame_interval()
142 struct usb_hcd *hcd = mtk->hcd; in xhci_mtk_set_frame_interval()
145 if (!of_device_is_compatible(dev->of_node, "mediatek,mt8195-xhci")) in xhci_mtk_set_frame_interval()
148 value = readl(hcd->regs + HFCNTR_CFG); in xhci_mtk_set_frame_interval()
151 writel(value, hcd->regs + HFCNTR_CFG); in xhci_mtk_set_frame_interval()
153 value = readl(hcd->regs + LS_EOF_CFG); in xhci_mtk_set_frame_interval()
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/linux/drivers/usb/cdns3/
H A Dcdnsp-gadget.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 #include <linux/io-64-nonatomic-lo-hi.h>
19 /* Max number slots - only 1 is allowed. */
43 * struct cdnsp_cap_regs - CDNSP Registers.
46 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
47 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
48 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
49 * @hcc_params: HCCPARAMS - Capability Parameters
50 * @db_off: DBOFF - Doorbell array offset
51 * @run_regs_off: RTSOFF - Runtime register space offset
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/linux/drivers/usb/gadget/udc/
H A Dtegra-xudc.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (c) 2013-2022, NVIDIA CORPORATION. All rights reserved.
12 #include <linux/dma-mapping.h>
246 return (le32_to_cpu(ctx->member) >> (shift)) & (mask); \
253 tmp = le32_to_cpu(ctx->member) & ~((mask) << (shift)); \
255 ctx->member = cpu_to_le32(tmp); \
262 BUILD_EP_CONTEXT_RW(interval, info0, 16, 0xff)
338 return (le32_to_cpu(trb->member) >> (shift)) & (mask); \
345 tmp = le32_to_cpu(trb->member) & ~((mask) << (shift)); \
347 trb->member = cpu_to_le32(tmp); \
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