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Searched +full:i2c +full:- +full:scl +full:- +full:clk +full:- +full:low +full:- +full:timeout +full:- +full:us (Results 1 – 21 of 21) sorted by relevance

/linux/drivers/i2c/busses/
H A Di2c-davinci.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * TI DAVINCI I2C adapter driver.
10 * ----------------------------------------------------------------------------
12 * ----------------------------------------------------------------------------
15 #include <linux/clk.h>
21 #include <linux/i2c.h>
32 /* ----- global defines ----------------------------------------------- */
94 /* set SDA and SCL as GPIO */
97 /* set SCL as output when used as GPIO*/
102 /* read SCL GPIO level */
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H A Di2c-exynos5.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * i2c-exynos5.c - Samsung Exynos5 I2C Controller Driver
11 #include <linux/i2c.h>
18 #include <linux/clk.h>
184 struct clk *clk; /* operating clock */ member
185 struct clk *pclk; /* bus clock */
206 /* Version of HS-I2C Hardware */
211 * struct exynos_hsi2c_variant - platform specific HSI2C driver data
213 * @hw: the hardware variant of Exynos I2C controller
251 .compatible = "samsung,exynos5-hsi2c",
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H A Di2c-hisi.c1 // SPDX-License-Identifier: GPL-2.0
3 * HiSilicon I2C Controller Driver for Kunpeng SoC
10 #include <linux/clk.h>
12 #include <linux/i2c.h>
94 struct clk *clk; member
108 /* I2C bus configuration */
116 writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_MASK); in hisi_i2c_enable_int()
121 writel_relaxed((~mask) & HISI_I2C_INT_ALL, ctlr->iobase + HISI_I2C_INT_MASK); in hisi_i2c_disable_int()
126 writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_CLR); in hisi_i2c_clear_int()
131 writel_relaxed(mask, ctlr->iobase + HISI_I2C_TX_INT_CLR); in hisi_i2c_clear_tx_int()
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H A Di2c-rcar.c1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for the Renesas R-Car I2C unit
5 * Copyright (C) 2014-19 Wolfram Sang <wsa@sang-engineering.com>
6 * Copyright (C) 2011-2019 Renesas Electronics Corporation
8 * Copyright (C) 2012-14 Renesas Solutions Corp.
11 * This file is based on the drivers/i2c/busses/i2c-sh7760.c
12 * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
15 #include <linux/clk.h>
18 #include <linux/dma-mapping.h>
23 #include <linux/i2c.h>
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H A Di2c-designware-common.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Synopsys DesignWare I2C adapter driver.
5 * Based on the TI DAVINCI I2C adapter driver.
15 #include <linux/clk.h>
21 #include <linux/i2c.h>
35 #include "i2c-designware-core.h"
65 "incorrect slave-transmitter mode configuration",
72 *val = readl(dev->base + reg); in dw_reg_read()
81 writel(val, dev->base + reg); in dw_reg_write()
90 *val = swab32(readl(dev->base + reg)); in dw_reg_read_swab()
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H A Di2c-sh_mobile.c1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH Mobile I2C Controller
5 * Copyright (C) 2014-19 Wolfram Sang <wsa@sang-engineering.com>
8 * Portions of the code based on out-of-tree driver i2c-sh7343.c
12 #include <linux/clk.h>
15 #include <linux/dma-mapping.h>
17 #include <linux/i2c.h>
41 /* ICIC: -DTE */
48 /* ICIC: -DTE */
52 /* 3 bytes or more, +---------+ gets repeated */
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H A Di2c-meson.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * I2C bus driver for Amlogic Meson SoCs
9 #include <linux/clk.h>
11 #include <linux/i2c.h>
21 /* Meson I2C register map */
68 * struct meson_i2c - Meson I2C device private data
70 * @adap: I2C adapter instance
73 * @clk: Pointer to clock structure
74 * @msg: Pointer to the current I2C message
90 struct clk *clk; member
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H A Di2c-pxa.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * I2C adapter for the PXA I2C bus access.
8 * Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
13 * Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
14 * Jan 2003: added limited signal handling [Kai-Uwe Bloem]
19 #include <linux/clk.h>
24 #include <linux/i2c.h>
34 #include <linux/platform_data/i2c-pxa.h>
38 /* I2C register field definitions */
59 #define ICR_A3700_FM (1 << 16) /* fast mode for armada-3700 */
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H A Di2c-uniphier-f.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk.h>
7 #include <linux/i2c.h>
25 #define UNIPHIER_FI2C_LCTL 0x14 /* clock low period control */
54 #define UNIPHIER_FI2C_BM_SCLO BIT(1) /* output for SCL line */
55 #define UNIPHIER_FI2C_BM_SCLS BIT(0) /* readback of SCL line */
63 #define UNIPHIER_FI2C_BRST_RSCL BIT(0) /* release SCL */
82 struct clk *clk; member
99 * TX-FIFO stores target address in it for the first access. in uniphier_fi2c_fill_txfifo()
103 fifo_space--; in uniphier_fi2c_fill_txfifo()
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H A Di2c-mxs.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale MXS I2C bus driver
5 * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
6 * Copyright (C) 2011-2012 Wolfram Sang, Pengutronix e.K.
8 * based on a (non-working) driver which was:
10 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
16 #include <linux/i2c.h>
25 #include <linux/dma-mapping.h>
27 #include <linux/dma/mxs-dma.h>
29 #define DRIVER_NAME "mxs-i2c"
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H A Di2c-stm32f7.c1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for STMicroelectronics STM32F7 I2C controller
5 * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc
14 * This driver is based on i2c-stm32f4.c
17 #include <linux/clk.h>
20 #include <linux/i2c.h>
21 #include <linux/i2c-smbus.h>
38 #include "i2c-stm32.h"
40 /* STM32F7 I2C registers */
52 /* STM32F7 I2C control 1 */
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H A Di2c-aspeed.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Aspeed 24XX/25XX I2C Controller.
5 * Copyright (C) 2012-2017 ASPEED Technology Inc.
10 #include <linux/clk.h>
14 #include <linux/i2c.h>
28 /* I2C Register */
39 /* 0x00 : I2C Interrupt Status Register */
40 /* 0x08 : I2C Interrupt Target Assignment */
163 /* Multi-master */
176 bus->master_state = ASPEED_I2C_MASTER_STOP; in aspeed_i2c_do_stop()
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H A Di2c-mpc.c1 // SPDX-License-Identifier: GPL-2.0
3 * This is a combined i2c adapter and algorithm driver for the
5 * the same I2C unit (8240, 8245, 85xx).
7 * Copyright (C) 2003-2004 Humboldt Solutions Ltd, adrian@humboldt.co.uk
21 #include <linux/clk.h>
25 #include <linux/i2c.h>
109 void (*setup)(struct device_node *node, struct mpc_i2c *i2c, u32 clock);
112 static inline void writeccr(struct mpc_i2c *i2c, u32 x) in writeccr() argument
114 writeb(x, i2c->base + MPC_I2C_CR); in writeccr()
122 static void mpc_i2c_fixup(struct mpc_i2c *i2c) in mpc_i2c_fixup() argument
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H A Di2c-npcm7xx.c1 // SPDX-License-Identifier: GPL-2.0
3 * Nuvoton NPCM7xx I2C Controller driver
8 #include <linux/clk.h>
11 #include <linux/i2c.h>
29 * External I2C Interface driver xfer indication values, which indicate status
58 /* I2C Bank (module had 2 banks of registers) */
64 /* Internal I2C states values (for the I2C module state machine). */
119 #define NPCM_I2CSCLLT 0x1C /* SCL Low Time */
121 #define NPCM_I2CSCLHT 0x1E /* SCL High Time */
125 #define NPCM_I2CTXF_CTL 0x12 /* Tx-FIFO Control */
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H A Di2c-s3c2410.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* linux/drivers/i2c/busses/i2c-s3c2410.c
7 * S3C2410 I2C Controller
13 #include <linux/i2c.h>
22 #include <linux/clk.h>
34 #include <linux/platform_data/i2c-s3c2410.h>
81 /* Max time to wait for bus to become idle after a xfer (in us) */
87 /* i2c controller state */
112 struct clk *clk; member
125 .name = "s3c2410-i2c",
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H A Di2c-imx.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2002 Motorola GSG-China
9 * Implementation of I2C Adapter/Algorithm Driver
10 * for I2C Bus integrated in Freescale i.MX/MXC processors
12 * Derived from Motorola GSG China I2C example driver
25 #include <linux/clk.h>
28 #include <linux/dma-mapping.h>
34 #include <linux/i2c.h>
46 #include <linux/platform_data/i2c-imx.h>
53 #define DRIVER_NAME "imx-i2c"
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H A Di2c-cadence.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * I2C bus driver for the Cadence I2C controller.
5 * Copyright (C) 2009 - 2014 Xilinx, Inc.
8 #include <linux/clk.h>
10 #include <linux/i2c.h>
21 /* Register offsets for the I2C device. */
24 #define CDNS_I2C_ADDR_OFFSET 0x08 /* I2C Address Register, RW */
25 #define CDNS_I2C_DATA_OFFSET 0x0C /* I2C Data Register, RW */
60 * I2C Address Register Bit mask definitions
62 * bits. A write access to this register always initiates a transfer if the I2C
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/linux/arch/arm/boot/dts/st/
H A Dstm32mp157c-emstamp-argon.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 #include "stm32mp15-pinctrl.dtsi"
10 #include "stm32mp15xxac-pinctrl.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/mfd/st,stpmic1.h>
23 stdout-path = "serial0:115200n8";
31 reserved-memory {
32 #address-cells = <1>;
33 #size-cells = <1>;
37 compatible = "shared-dma-pool";
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/linux/drivers/i2c/
H A Di2c-core-base.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Linux I2C core
5 * Copyright (C) 1995-99 Simon G. Vogl
10 * Copyright (C) 2013-2017 Wolfram Sang <wsa@kernel.org>
13 #define pr_fmt(fmt) "i2c-core: " fmt
15 #include <dt-bindings/i2c/i2c.h>
17 #include <linux/clk/clk-conf.h>
24 #include <linux/i2c.h>
25 #include <linux/i2c-smbus.h>
46 #include "i2c-core.h"
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/linux/drivers/i3c/master/
H A Dsvc-i3c-master.c1 // SPDX-License-Identifier: GPL-2.0
3 * Silvaco dual-role I3C master driver
11 #include <linux/clk.h>
157 * corrupted and results in a no repeated-start condition at the end of
195 * struct svc_i3c_master - Silvaco I3C Master structure
203 * @hj_work: Hot-join work
233 struct clk *fclk;
255 * struct svc_i3c_i2c_dev_data - Device specific data
268 return (master->drvdata->quirks & quirk); in svc_has_quirk()
273 return ((master->drvdata->quirks & SVC_I3C_QUIRK_DAA_CORRUPT) && in svc_has_daa_corrupt()
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/linux/drivers/media/dvb-frontends/drx39xyj/
H A Ddrxj.c2 Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
52 /*-----------------------------------------------------------------------------
54 ----------------------------------------------------------------------------*/
75 #define DRX39XX_MAIN_FIRMWARE "dvb-fe-drxj-mc-1.0.8.fw"
201 /*-----------------------------------------------------------------------------
203 ----------------------------------------------------------------------------*/
205 /*-----------------------------------------------------------------------------
207 ----------------------------------------------------------------------------*/
209 #define DRXJ_WAKE_UP_KEY (demod->my_i2c_dev_addr->i2c_addr)
214 * \brief Default I2C address of a demodulator instance.
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