| /linux/net/vmw_vsock/ |
| H A D | hyperv_transport.c | 251 struct hvsock *hvs = vsk->trans; in hvs_channel_cb() local
252 struct vmbus_channel *chan = hvs->chan; in hvs_channel_cb()
303 struct hvsock *hvs = NULL; in hvs_open_connection() local
353 hvs = vsock_sk(sk)->trans; in hvs_open_connection()
354 hvs->chan = chan; in hvs_open_connection()
393 hvs->chan = NULL; in hvs_open_connection()
444 struct hvsock *hvs; in hvs_sock_init() local
447 hvs = kzalloc_obj(*hvs); in hvs_sock_init()
448 if (!hvs) in hvs_sock_init()
451 vsk->trans = hvs; in hvs_sock_init()
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| /linux/drivers/gpu/drm/vc4/ |
| H A D | vc4_plane.c | 9 * Each DRM plane is a layer of pixels being scanned out by the HVS.
11 * At atomic modeset check time, we compute the HVS display element
15 * into the region of the HVS that it has allocated for us.
36 u32 hvs; /* HVS_FORMAT_* */ member
43 .hvs = HVS_PIXEL_FORMAT_RGBA8888,
49 .hvs = HVS_PIXEL_FORMAT_RGBA8888,
55 .hvs = HVS_PIXEL_FORMAT_RGBA8888,
61 .hvs = HVS_PIXEL_FORMAT_RGBA8888,
67 .hvs = HVS_PIXEL_FORMAT_RGB565,
73 .hvs = HVS_PIXEL_FORMAT_RGB565,
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| H A D | vc4_kms.c | 138 struct vc4_hvs *hvs = vc4->hvs; in vc4_ctm_commit() local
214 struct vc4_hvs *hvs = vc4->hvs; in vc4_hvs_pv_muxing_commit() local
257 struct vc4_hvs *hvs = vc4->hvs; in vc5_hvs_pv_muxing_commit() local
333 struct vc4_hvs *hvs = vc4->hvs; in vc6_hvs_pv_muxing_commit() local
382 struct vc4_hvs *hvs = vc4->hvs; in vc4_atomic_commit_tail() local
407 vc4_hvs_mask_underrun(hvs, vc4_crtc_state->assigned_channel); in vc4_atomic_commit_tail()
434 500000000, hvs->max_core_rate); in vc4_atomic_commit_tail()
442 WARN_ON(clk_set_min_rate(hvs->core_clk, core_rate)); in vc4_atomic_commit_tail()
443 WARN_ON(clk_set_min_rate(hvs->disp_clk, core_rate)); in vc4_atomic_commit_tail()
485 hvs->max_core_rate, in vc4_atomic_commit_tail()
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| H A D | vc4_crtc.c | 12 * the HVS at that timing, and feeds it to the encoder.
16 * responsible for writing the display list for the HVS channel that
85 struct vc4_hvs *hvs = vc4->hvs; in vc4_crtc_get_cob_allocation() local
114 struct vc4_hvs *hvs = vc4->hvs; in vc4_crtc_get_scanout_position() local
132 * pixelvalve by the HVS, and also the scaler status. in vc4_crtc_get_scanout_position()
145 /* Vertical position of hvs composed scanline. */ in vc4_crtc_get_scanout_position()
158 if (vc4_hvs_get_fifo_frame_count(hvs, channel) % 2) in vc4_crtc_get_scanout_position()
163 /* This is the offset we need for translating hvs -> pv scanout pos. */ in vc4_crtc_get_scanout_position()
169 /* HVS more than fifo_lines into frame for compositing? */ in vc4_crtc_get_scanout_position()
173 * from HVS. The actual PV scanout can not trail behind more in vc4_crtc_get_scanout_position()
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| H A D | vc4_regs.h | 24 WARN_ON(!FIELD_FIT(hvs->vc4->gen == VC4_GEN_6_C ? \
27 FIELD_PREP(hvs->vc4->gen == VC4_GEN_6_C ? \
32 #define VC6_GET_FIELD(word, field) FIELD_GET(hvs->vc4->gen == VC4_GEN_6_C ? \
241 /* Global register for clock gating the HVS */
419 /* Last pixel in the COB (display FIFO memory) allocated to this HVS
425 /* First pixel in the COB (display FIFO memory) allocated to this HVS
520 /* Slave addresses for DMAing from HVS composition output to other
565 #define SCALER6_DISPX_CTRL0(x) ((hvs->vc4->gen == VC4_GEN_6_C) ? \
576 #define SCALER6_DISPX_CTRL1(x) ((hvs->vc4->gen == VC4_GEN_6_C) ? \
583 #define SCALER6_DISPX_BGND(x) ((hvs->vc4->gen == VC4_GEN_6_C) ? \
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| H A D | vc4_drv.c | 279 { .compatible = "brcm,bcm2711-hvs" },
280 { .compatible = "brcm,bcm2712-hvs" },
281 { .compatible = "brcm,bcm2835-hvs" },
428 * but after the HVS to set the possible_crtc field properly
429 * - The HDMI driver needs to be bound after the HVS so that we can
430 * lookup the HVS maximum core clock rate and figure out if we
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| H A D | vc4_hdmi.c | 442 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20) { in vc4_hdmi_connector_get_modes()
1730 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20 && clock > HDMI_14_MAX_TMDS_CLK) in vc4_hdmi_connector_clock_valid()
1734 if (!vc4->hvs->vc5_hdmi_enable_4096by2160 && in vc4_hdmi_connector_clock_valid()
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| /linux/Documentation/gpu/ |
| H A D | vc4.rst | 21 HVS section in Display Hardware Handling
25 :doc: VC4 HVS module.
27 HVS planes
73 * The HVS to PixelValve dynamic FIFO assignment, for the BCM2835-7
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| /linux/drivers/gpu/drm/vc4/tests/ |
| H A D | vc4_mock.c | 178 vc4->hvs = __vc4_hvs_alloc(vc4, NULL, NULL); in __mock_device()
179 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, vc4->hvs); in __mock_device()
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| /linux/Documentation/devicetree/bindings/display/ |
| H A D | brcm,bcm2835-vc4.yaml | 14 with HDMI output and the HVS (Hardware Video Scaler) for compositing
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| /linux/tools/testing/selftests/net/ |
| H A D | test_vxlan_under_vrf.sh | 7 # two for the HVs, two for the VMs.
91 # Check connectivity between HVs by pinging hv-2 from hv-1
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| H A D | test_vxlan_vnifiltering.sh | 7 # six namespaces: two for the HVs, four for the VMs. Each VM is
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| /linux/arch/arm/boot/dts/broadcom/ |
| H A D | bcm2711-rpi.dtsi | 71 &hvs {
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| H A D | bcm283x.dtsi | 431 hvs@7e400000 {
432 compatible = "brcm,bcm2835-hvs";
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| /linux/tools/testing/vsock/ |
| H A D | util.h | 16 x(HYPERV, "hvs")
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| /linux/drivers/clk/bcm/ |
| H A D | clk-raspberrypi.c | 86 * The clock is shared between the HVS and the CSI
88 * on the pixels composited on the HVS and the capture
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| /linux/arch/arm64/boot/dts/broadcom/ |
| H A D | bcm2712-rpi-5-b-base.dtsi | 233 &hvs {
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| /linux/drivers/net/ethernet/broadcom/bnx2x/ |
| H A D | bnx2x_vfpf.h | 29 /* Common definitions for all HVs */
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| /linux/arch/x86/kernel/ |
| H A D | irq.c | 166 seq_printf(p, "%*s: ", prec, "HVS"); in arch_show_interrupts()
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| /linux/include/uapi/drm/ |
| H A D | drm_fourcc.h | 1115 * HVS, it is only valid for H.264 (NV12/21) and RGBA modes.
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