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/linux/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/
H A D	mmu.json	9 "PublicDescription": "Data TLB translation cache hit on S1L2 walk cache entry", 12 "BriefDescription": "Data TLB translation cache hit on S1L2 walk cache entry" 15 "PublicDescription": "Data TLB translation cache hit on S1L1 walk cache entry", 18 "BriefDescription": "Data TLB translation cache hit on S1L1 walk cache entry" 21 "PublicDescription": "Data TLB translation cache hit on S1L0 walk cache entry", 24 "BriefDescription": "Data TLB translation cache hit on S1L0 walk cache entry" 27 "PublicDescription": "Data TLB translation cache hit on S2L2 walk cache entry", 30 "BriefDescription": "Data TLB translation cache hit on S2L2 walk cache entry" 33 "PublicDescrition": "Data TLB translation cache hit on S2L1 walk cache entry", 36 "BriefDescription": "Data TLB translation cache hit on S2L1 walk cache entry" [all …]
H A D	core-imp-def.json	15 "PublicDescription": "Predictable branch speculatively executed that hit any level of BTB", 18 "BriefDescription": "Predictable branch speculatively executed that hit any level of BTB" 21 …"PublicDescription": "Predictable conditional branch speculatively executed that hit any level of … 24 …"BriefDescription": "Predictable conditional branch speculatively executed that hit any level of B… 27 …"PublicDescription": "Predictable taken branch speculatively executed that hit any level of BTB th… 30 …"BriefDescription": "Predictable taken branch speculatively executed that hit any level of BTB tha… 33 …"PublicDescription": "Predictable taken branch speculatively executed that hit any level of BTB th… 36 …"BriefDescription": "Predictable taken branch speculatively executed that hit any level of BTB tha… 39 …tion": "Predictable unconditional branch speculatively executed that did not hit any level of BTB", 42 …ption": "Predictable unconditional branch speculatively executed that did not hit any level of BTB" [all …]
/linux/tools/perf/pmu-events/arch/x86/knightslanding/
H A D	cache.json	87 …"BriefDescription": "Counts the number of load micro-ops retired that hit in the L2 (Precise Event… 93 …"PublicDescription": "This event counts the number of load micro-uops retired that hit in the L2 (… 135 …refetch code read requests that accounts for responses from snoop request hit with data forwarded… 145 …fetch code read requests that accounts for responses from a snoop request hit with data forwarded… 155 …fetch code read requests that accounts for responses from a snoop request hit with data forwarded… 165 …refetch code read requests that accounts for responses from snoop request hit with data forwarded… 175 …fetch code read requests that accounts for responses from a snoop request hit with data forwarded… 185 …fetch code read requests that accounts for responses from a snoop request hit with data forwarded… 195 …e reads and prefetch code read requests that accounts for responses which hit its own tile's L2 w… 205 …e reads and prefetch code read requests that accounts for responses which hit its own tile's L2 w… [all …]
/linux/tools/perf/pmu-events/arch/x86/sandybridge/
H A D	cache.json	242 "BriefDescription": "Demand Data Read requests that hit L2 cache.", 250 "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache.", 266 "BriefDescription": "RFO requests that hit L2 cache.", 290 "BriefDescription": "RFOs that hit cache lines in E state.", 298 "BriefDescription": "RFOs that hit cache lines in M state.", 407 …"PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) an… 417 …"PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) an… 422 …"BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed… 450 …"BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due … 482 …"PublicDescription": "This event counts retired load uops that hit in the last-level (L3) cache wi… [all …]
/linux/tools/perf/pmu-events/arch/x86/goldmont/
H A D	cache.json	61 …ive loads are ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, … 77 "BriefDescription": "Load uops retired that hit L1 data cache (Precise event capable)", 83 "PublicDescription": "Counts load uops retired that hit the L1 data cache.", 99 "BriefDescription": "Load uops retired that hit L2 (Precise event capable)", 105 "PublicDescription": "Counts load uops retired that hit in the L2 cache.", 121 "BriefDescription": "Loads retired that hit WCB (Precise event capable)", 127 …ess of requesting the data. When load Y requests the data, it will either hit the WCB, or the L1 … 217 "BriefDescription": "Counts data reads (demand & prefetch) that hit the L2 cache.", 223 …"PublicDescription": "Counts data reads (demand & prefetch) that hit the L2 cache. Requires MSR_OF… 239 …"Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other proces… [all …]
/linux/tools/perf/pmu-events/arch/x86/haswell/
H A D	virtual-memory.json	21 …"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not … 30 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)", 34 …t counts load operations from a 2M page that miss the first DTLB level but hit the second and do n… 39 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)", 43 …t counts load operations from a 4K page that miss the first DTLB level but hit the second and do n… 110 …"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not … 114 …"PublicDescription": "Store operations that miss the first TLB level but hit the second and do not… 119 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M)", 123 … counts store operations from a 2M page that miss the first DTLB level but hit the second and do n… 128 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K)", [all …]
H A D	cache.json	57 "BriefDescription": "Not rejected writebacks that hit L2 cache", 61 "PublicDescription": "Not rejected writebacks that hit L2 cache.", 181 "PublicDescription": "Number of instruction fetches that hit the L2 cache.", 195 "BriefDescription": "Demand Data Read requests that hit L2 cache", 200 …Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache", 215 "BriefDescription": "L2 prefetch requests that hit L2 cache", 219 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", 253 "BriefDescription": "RFO requests that hit L2 cache", 257 "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.", 392 …"BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed … [all …]
/linux/tools/perf/pmu-events/arch/x86/haswellx/
H A D	virtual-memory.json	21 …"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not … 30 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)", 34 …t counts load operations from a 2M page that miss the first DTLB level but hit the second and do n… 39 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)", 43 …t counts load operations from a 4K page that miss the first DTLB level but hit the second and do n… 110 …"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not … 114 …"PublicDescription": "Store operations that miss the first TLB level but hit the second and do not… 119 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M)", 123 … counts store operations from a 2M page that miss the first DTLB level but hit the second and do n… 128 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K)", [all …]
H A D	cache.json	57 "BriefDescription": "Not rejected writebacks that hit L2 cache", 61 "PublicDescription": "Not rejected writebacks that hit L2 cache.", 181 "PublicDescription": "Number of instruction fetches that hit the L2 cache.", 195 "BriefDescription": "Demand Data Read requests that hit L2 cache", 200 …Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache", 215 "BriefDescription": "L2 prefetch requests that hit L2 cache", 219 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", 253 "BriefDescription": "RFO requests that hit L2 cache", 257 "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.", 392 …"BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed … [all …]
/linux/tools/perf/pmu-events/arch/x86/rocketlake/
H A D	cache.json	45 …hit at least once by demand. The valid outstanding interval is defined until the FB deallocation b… 109 …quests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. O… 159 "BriefDescription": "Demand Data Read requests that hit L2 cache", 163 …"Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.", 195 "BriefDescription": "RFO requests that hit L2 cache", 199 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", 213 "BriefDescription": "SW prefetch requests that hit L2 cache.", 217 …"PublicDescription": "Counts Software prefetch requests that hit the L2 cache. Accounts for PREFET… 349 …"BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop… 354 …"PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cros… [all …]
/linux/tools/perf/pmu-events/arch/x86/icelake/
H A D	cache.json	45 …hit at least once by demand. The valid outstanding interval is defined until the FB deallocation b… 109 …quests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. O… 159 "BriefDescription": "Demand Data Read requests that hit L2 cache", 163 …"Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.", 195 "BriefDescription": "RFO requests that hit L2 cache", 199 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", 213 "BriefDescription": "SW prefetch requests that hit L2 cache.", 217 …"PublicDescription": "Counts Software prefetch requests that hit the L2 cache. Accounts for PREFET… 349 …"BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop… 354 …"PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cros… [all …]
/linux/tools/perf/pmu-events/arch/x86/alderlaken/
H A D	cache.json	11 "BriefDescription": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a per core basis.", 14 "EventName": "L2_REQUEST.HIT", 15 "PublicDescription": "Counts the number of L2 Cache accesses that resulted in a hit from a front door request only (does not include rejects or recycles), Counts on a per core basis.", 47 "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", 51 "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or translation lookaside buffer (TLB) miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", 56 "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DRAM).", 60 "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or translation lookaside buffer (TLB) miss which hit in DRAM or MMIO (non-DRAM).", 65 "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.", 69 "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache.", 74 "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit i [all...]
/linux/tools/perf/pmu-events/arch/x86/amdzen3/
H A D	cache.json	41 …n). L2 Prefetcher. All prefetches accepted by L2 pipeline, hit or miss. Types of PF and L2 hit/mis… 136 … L2 cacheable request access status (not including L2 Prefetch). Data cache shared read hit in L2", 142 …cheable request access status (not including L2 Prefetch). Data cache read hit in L2. Modifiable.", 148 …cheable request access status (not including L2 Prefetch). Data cache read hit non-modifiable line… 154 …le request access status (not including L2 Prefetch). Data cache store or state change hit in L2.", 166 …eable request access status (not including L2 Prefetch). Instruction cache hit modifiable line in … 172 …eable request access status (not including L2 Prefetch). Instruction cache hit non-modifiable line… 196 …us (not including L2 Prefetch). Instruction cache request hit in L2 and Data cache request hit in … 208 "BriefDescription": "L2 prefetch hit in L2. Use l2_cache_hits_from_l2_hwpf instead.", 214 … L3. Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit the L3.", [all …]
/linux/tools/perf/pmu-events/arch/x86/ivytown/
H A D	cache.json	207 "PublicDescription": "Number of instruction fetches that hit the L2 cache.", 221 "BriefDescription": "Demand Data Read requests that hit L2 cache", 225 "PublicDescription": "Demand Data Read requests that hit L2 cache.", 230 "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache", 234 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", 248 "BriefDescription": "RFO requests that hit L2 cache", 252 "PublicDescription": "RFO requests that hit L2 cache.", 275 "BriefDescription": "RFOs that hit cache lines in M state", 279 "PublicDescription": "RFOs that hit cache lines in M state.", 410 …"BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed… [all …]
/linux/tools/perf/pmu-events/arch/x86/elkhartlake/
H A D	cache.json	36 …"BriefDescription": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a pe… 39 "EventName": "L2_REQUEST.HIT", 40 …"PublicDescription": "Counts the number of L2 Cache accesses that resulted in a hit from a front d… 81 …f cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2, LLC, DRA… 85 …e to an instruction cache or translation lookaside buffer (TLB) miss which hit in the L2, LLC, DRA… 90 …f cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (No… 94 …e to an instruction cache or translation lookaside buffer (TLB) miss which hit in DRAM or MMIO (no… 99 … of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.", 103 …due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache.", 108 …f cycles the core is stalled due to an instruction cache or TLB miss which hit in the LLC or other… [all …]
/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A D	cache.json	36 …"BriefDescription": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a pe… 39 "EventName": "L2_REQUEST.HIT", 40 …"PublicDescription": "Counts the number of L2 Cache accesses that resulted in a hit from a front d… 81 …f cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2, LLC, DRA… 85 …e to an instruction cache or translation lookaside buffer (TLB) miss which hit in the L2, LLC, DRA… 90 …f cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (No… 94 …e to an instruction cache or translation lookaside buffer (TLB) miss which hit in DRAM or MMIO (no… 99 … of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.", 103 …due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache.", 108 …f cycles the core is stalled due to an instruction cache or TLB miss which hit in the LLC or other… [all …]
/linux/tools/perf/pmu-events/arch/x86/graniterapids/
H A D	cache.json	53 "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", 108 "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.REFERENCES]", 113 "BriefDescription": "All requests that hit L2 cache. [This event is alias to L2_RQSTS.HIT]", 116 "EventName": "L2_REQUEST.HIT", 117 "PublicDescription": "Counts all requests that hit L2 cache. [This event is alias to L2_RQSTS.HIT]", 144 "PublicDescription": "Counts Demand Data Read requests accessing the L2 cache. These requests may hit or miss L2 cache. True-miss exclude misses that were merged with ongoing L2 misses. An access is counted once.", 202 "BriefDescription": "Demand Data Read requests that hit L [all...]
/linux/tools/perf/pmu-events/arch/x86/emeraldrapids/
H A D	cache.json	3 "BriefDescription": "Hit snoop reply with data, line invalidated.", 21 "BriefDescription": "Hit snoop reply without sending the data, line invalidated.", 39 "BriefDescription": "Hit snoop reply with data, line kept in Shared state.", 57 "BriefDescription": "Hit snoop reply without sending the data, line kept in Shared state.", 125 "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", 180 "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.REFERENCES]", 185 "BriefDescription": "All requests that hit L2 cache [This event is alias to L2_RQSTS.HIT]", 188 "EventName": "L2_REQUEST.HIT", [all...]
/linux/tools/perf/pmu-events/arch/arm64/ampere/emag/
H A D	cache.json	132 "PublicDescription": "Page walk cache level-0 stage-1 hit", 135 "BriefDescription": "Page walk, L0 stage-1 hit" 138 "PublicDescription": "Page walk cache level-1 stage-1 hit", 141 "BriefDescription": "Page walk, L1 stage-1 hit" 144 "PublicDescription": "Page walk cache level-2 stage-1 hit", 147 "BriefDescription": "Page walk, L2 stage-1 hit" 150 "PublicDescription": "Page walk cache level-1 stage-2 hit", 153 "BriefDescription": "Page walk, L1 stage-2 hit" 156 "PublicDescription": "Page walk cache level-2 stage-2 hit", 159 "BriefDescription": "Page walk, L2 stage-2 hit"
/linux/tools/perf/pmu-events/arch/x86/goldmontplus/
H A D	cache.json	61 …ive loads are ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, … 77 "BriefDescription": "Load uops retired that hit L1 data cache (Precise event capable)", 83 "PublicDescription": "Counts load uops retired that hit the L1 data cache.", 99 "BriefDescription": "Load uops retired that hit L2 (Precise event capable)", 105 "PublicDescription": "Counts load uops retired that hit in the L2 cache.", 121 "BriefDescription": "Loads retired that hit WCB (Precise event capable)", 127 …ess of requesting the data. When load Y requests the data, it will either hit the WCB, or the L1 … 228 "BriefDescription": "Counts data reads (demand & prefetch) hit the L2 cache.", 234 …"PublicDescription": "Counts data reads (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE… 239 …on": "Counts data reads (demand & prefetch) miss the L2 cache with a snoop hit in the other proces… [all …]
/linux/tools/perf/pmu-events/arch/x86/jaketown/
H A D	cache.json	242 "BriefDescription": "Demand Data Read requests that hit L2 cache.", 250 "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache.", 266 "BriefDescription": "RFO requests that hit L2 cache.", 290 "BriefDescription": "RFOs that hit cache lines in E state.", 298 "BriefDescription": "RFOs that hit cache lines in M state.", 406 …"PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) an… 415 …"PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) an… 420 …"BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed… 452 …"BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due … 483 …"PublicDescription": "This event counts retired load uops that hit in the last-level (L3) cache wi… [all …]
/linux/tools/perf/pmu-events/arch/x86/sapphirerapids/
H A D	cache.json	3 "BriefDescription": "Hit snoop reply with data, line invalidated.", 21 "BriefDescription": "Hit snoop reply without sending the data, line invalidated.", 39 "BriefDescription": "Hit snoop reply with data, line kept in Shared state.", 57 "BriefDescription": "Hit snoop reply without sending the data, line kept in Shared state.", 125 "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", 180 "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.REFERENCES]", 185 "BriefDescription": "All requests that hit L2 cache [This event is alias to L2_RQSTS.HIT]", 188 "EventName": "L2_REQUEST.HIT", [all...]
/linux/tools/perf/pmu-events/arch/x86/meteorlake/
H A D	cache.json	77 "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", 207 "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.REFERENCES]", 213 "BriefDescription": "Counts the number of L2 Cache Accesses that resulted in a Hit from a front door request only (does not include rejects or recycles), per core event", 216 "EventName": "L2_REQUEST.HIT", 222 "BriefDescription": "All requests that hit L2 cache. [This event is alias to L2_RQSTS.HIT]", 225 "EventName": "L2_REQUEST.HIT", 226 "PublicDescription": "Counts all requests that hit L2 cache. [This event is alias to L2_RQSTS.HIT]", [all...]
/linux/tools/perf/pmu-events/arch/x86/sierraforest/
H A D	cache.json	82 "BriefDescription": "Counts the number of L2 Cache Accesses that resulted in a Hit from a front door request only (does not include rejects or recycles), per core event", 85 "EventName": "L2_REQUEST.HIT", 132 "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.", 136 "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache.", 141 "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an ICACHE or ITLB miss which hit in the LLC. If the core has access to an L3 cache, an LLC hit refers to an L3 cache hit, otherwise it counts zeros.", 165 "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache.", 169 "PublicDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the L2 cache.", 182 "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit i [all...]
/linux/tools/perf/pmu-events/arch/s390/cf_z16/
H A D	extended.json	111 "BriefDescription": "Directory Write Level 1 Data Cache from L2-Cache with Chip HP Hit", 112 …rced from the requestors Level-2 cache after using chip level horizontal persistence, Chip-HP hit." 118 "BriefDescription": "Directory Write Level 1 Data Cache from L2-Cache with Drawer HP Hit", 119 … from the requestors Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit." 139 "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip L2-Cache with Chip HP Hit", 140 … sourced from an On-Chip Level-2 cache after using chip level horizontal persistence, Chip-HP hit." 146 "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip L2-Cache with Drawer HP Hit", 147 …as sourced from an On-Chip Level-2 cache using drawer level horizontal persistence, Drawer-HP hit." 209 … "Directory Write Level 1 Instruction and Data Cache from On-Module Memory L2-Cache with Chip Hit", 210 …e line was sourced from an On-Module Level-2 cache using chip horizontal persistence, Chip-HP hit." [all …]

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